Description of Contex-M3 registers in STM32

        Three structures are defined in the STM32 firmware library to correspond to these three register groups. The correspondence between these three structures and the registers in the ARM manual is as follows:

 
1. NVIC register group
The STM32 firmware library has the following definitions:
typedef struct
{
  vu32 ISER[2];
  u32 RESERVED0[30];
  vu32 ICER[2];
  u32 RSERVED1[30];
  vu32 ISPR[2];
  u32 RESERVED2[30];
  vu32 ICPR[2];
  u32 RESERVED3[30];
  vu32 IABR[2];
  u32 RESERVED4[62];
  vu32 IPR[11];
} NVIC_TypeDef;
 
Their corresponding names in the ARM manual are
ISER = Interrupt Set-Enable Registers
ICER = Interrupt Clear-Enable Registers
ISPR = Interrupt Set-Pending Register
ICPR = Interrupt Clear-Pending Register
IABR = Active Bit Register
IPR = Interrupt Priority Registers
 
Each register has 240 bits, starting with Interrupt Set-Enable Register. Registers description: ISER[0] corresponds to interrupt sources 0~31, ISER[1] corresponds to interrupt sources 32~63. STM32 has only 60 interrupt sources, so there is no ISER[2:7].
 
Referring to the interrupt vector table in the STM32 technical reference manual, the locations of the interrupt sources are:
Position 0 - WWDG = Window Watchdog interrupt
Position 1 - PVD = PVD through EXTI Line detection interrupt
Position 2 - TAMPER = Tamper interrupt
......
Position 58 - DMA2_Channel3 = DMA2 Channel3 global interrupt
Position 59 - DMA2_Channel4_5 = DMA2 Channel4 and DMA2 Channel5 global interrupts
 
2. System control register group The
STM32 firmware library has the following definitions:
typedef struct
{
  vuc32 CPUID;
  vu32 ICSR;
  vu32 VTOR;
  vu32 AIRCR;
  vu32 SCR;
  vu32 CCR;
  vu32 SHPR[3];
  vu32 SHCSR;
  vu32 CFSR;
  vu32 HFSR;
  vu32 DFSR;
  vu32 MMFAR;
  vu32 BFAR;
  vu32 AFSR;
} SCB_TypeDef; /* System Control Block Structure */
 
Their corresponding names in the ARM manual are
CPUID = CPUID Base Register
ICSR = Interrupt Control State Register
VTOR = Vector Table Offset Register
AIRCR = Application Interrupt/Reset Control Register
SCR = System Control Register
CCR = Configuration Control Register
SHPR = System Handlers Priority Register
SHCSR = System Handler Control and State Register
CFSR = Configurable Fault Status Registers
HFSR = Hard Fault Status Register
DFSR = Debug Fault Status Register
MMFAR = Mem Manage Address Register
BFAR = Bus Fault Address Register
AFSR = Auxiliary Fault Status Register3
 
. System clock register group The
STM32 firmware library has the following definitions:
typedef struct
{
  vu32 CTRL;
  vu32 LOAD;
  vu32 VAL;
  vuc32 CALIB;
} SysTick_TypeDef;
 
Their corresponding names in the ARM manual are
CTRL = SysTick Control and Status Register
LOAD = SysTick Reload Value Register
VAL = SysTick Current Value Register
CALIB = SysTick Calibration Value Register