SDRAM driver for S3C2440

S3C2440 leads out 27 address lines ADDR0~ADDR26, which can address up to 128MB, and the addressing space of S3C2440 can reach 1GB, because S3C2440 divides the 1GB address space into 8 BANKS (Bank0~Bank7), each of which corresponds to a chip select signal line nGCS0~nGCS7. When accessing BANKx, the nGCSx pin level is pulled low to select the external device. S3C2440 can access 1GB through 8 select signal lines and 27 address lines. As shown in Figure 2-48.

Figure 2-48 S3C2440 memory bank

As shown in the figure, the left side of the figure corresponds to the memory bank distribution diagram when Nandflash is not used for startup (through jumper settings). Usually, Norflash startup is selected in this startup mode, and Norflash is soldered to Bank0. After the system is powered on, the CPU starts to fetch instructions from the starting address 0x00000000 of Bank0.

The right side of the above picture shows the selection of booting from Nandflash (set by jumper). After the system is powered on, the CPU will automatically copy the first 4K data in Nandflash to a 4K SRAM type memory inside the S3C2440 (called Steppingstone), and then fetch instructions from Steppingstone to start.

Bank0~Bank5 can be soldered with ROM or SRAM type memory, and Bank6~Bank7 can be soldered with ROM, SRAM, SDRAM type memory. That is to say, the SDRAM memory of S3C2440 should be soldered on Bank6~Bank7, and the maximum supported memory is 256M. Bank0~Bank5 are usually soldered with some small-capacity ROM for booting the system. What kind of memory is soldered and how much capacity it has varies according to each development board manufacturer. For example, the MINI2440 development board solders 2M Norflash on Bank0 to store the system boot program Bootloader, and solders two 32M, 16Bit wide SDRAM memories on Bank6 and Bank7, which are connected in parallel to form 64M, 32-bit memory.

Since S3C2440 is a 32-bit chip, theoretically it can reach an addressing range of 4GB. In addition to the above 8 banks used to connect external devices, a part of the address space is used for device special function registers, and the remaining addresses are not used.

Table 2-14 S3C2440 device register address space

1.1.2 How SDRAM works

The inside of SDRAM is a storage array. The array is like a table, and data is "filled" into it. When reading and writing data, it is the same as the retrieval principle of a table. First specify a row (Row), then specify a column (Column), and we can accurately find the required cell. This is the basic principle of memory chip addressing, as shown in Figure 2-49.

Figure 2-49 Schematic diagram of memory row and column addressing

This cell (storage array) is called a logical bank (Logical Bank, hereinafter referred to as L-Bank). Due to technical and cost reasons, it is impossible to make only one full-capacity L-Bank, and most importantly, due to the limitations of the working principle of SDRAM, a single L-Bank will cause very serious addressing conflicts and greatly reduce memory efficiency. Therefore, people divide the SDRAM into multiple L-Banks, currently basically 4 (this is also the maximum number of L-Banks in the SDRAM specification). It can be seen that when addressing, you must first determine which L-Bank, and then select the corresponding rows and columns in this selected L-Bank for addressing. Therefore, when accessing the memory, only one L-Bank can work at a time. As shown in Figure 2-50:

Figure 2-50 Memory storage unit

When operating the memory (see the figure below), you must first determine the L-Bank to operate, so you must select the L-Bank. There are two more pins BA0 and BA1 on the external pins of the memory chip, which are used to select 4 L-Banks. As mentioned earlier, the 32-bit address length is divided into row address and column address due to its storage structure characteristics. From the memory structure diagram below, we can see that there are only 13 address lines A0~A12 on the external pin address lines of the memory, which can only address 8M memory space at most. What mechanism is used to address 64M memory space? The row address line and column address line of SDRAM are time-division multiplexed, that is, the address is sent out twice, first the row address (nSRAS row valid operation), and then the column address (nSCAS column valid operation). In this way, the number of address lines can be greatly reduced, and the performance of the device and the complexity of the manufacturing process can be improved. But the addressing process will also become complicated. In fact, the current SDRAM generally uses L-Bank as the basic addressing object. The selection between L-Banks is controlled by the L-Bank address line BAn. The row address line and column address line connect all L-Banks. The width of the data in each L-Bank is the same as the width of the entire memory. In this way, the data storage speed can be accelerated. At the same time, BAn can also make the unselected L-Bank work in low power mode, thereby reducing the power consumption of the device.

Figure 2-51 HY57561620 internal structure

Development board memory controller pin wiring (taking MINI2440 development board as an example):

(1) Determine the wiring of BA0 and BA1

Table 2-15 BA0, BA1 wiring

Bank Size: External memory capacity (HY57561620 is 4Mbit*16bit*4Bank*2Chips/8=64MB)

Bus Width: Bus width (two 16-bit HY57561620 chips, connected in parallel to 32 bits)
Base Component: Single chip capacity (bit) (256Mb)
Memory Configuration: Memory configuration (（4M*16*4banks）*2Chips )

From the Bank Address pin connection configuration table in the hardware manual, we can see that the two address lines A[25:24] are used as Bank chip select signals. Just two wires can select the four banks of each storage unit.

(2) Determine other wiring

The SDRAM memory is soldered on BANK6~BANK7, and its soldering pins are shown in Figure 2-52:

Figure 2-52 S3C2440 16-bit wide memory chip

The above figure is a schematic diagram of the parallel connection of two 16-bit chips provided by S3C2440. An is the CPU address bus, among which A2~A14 is the memory chip addressing bus. The address addressing bus starts from A2 because the memory addresses are all byte-aligned. A24 and A25 are L-Bank chip select signals, Dn is the CPU data bus, and the others are corresponding control signal lines.

Table 2-16 Memory chip pin description

From the wiring diagram of the S3C2440 16-bit memory chip, we can see that the two memory chips are only different in two places: the wiring methods of LDQM, UDQM and data bus DQn are different.

Since the memory chip width is 16 bits, two bytes can be read at a time. However, the minimum addressing unit in the operating system is usually 1 byte, so the memory controller must ensure that every byte in the memory can be accessed. UDQM and LDQM represent the high and low byte read signals of 16-bit data respectively.

When reading data, LDQM /UDQM are used to control whether the high and low bytes in the 16-bit data can be read. When LDQM /UDQM is low, the corresponding high/low bytes can be read. If LDQM /UDQM is high, the corresponding high/low bytes cannot be read.

When writing data to the memory, LDQM /UDQM controls whether the data can be written. When LDQM /UDQM is low, the corresponding high/low bytes can be written. If LDQM /UDQM is high, the corresponding high/low bytes cannot be written. By controlling the LDQM /UDQM signal, the data stored in the two memory chips can be controlled. Since the address lines of the two memory cells are common, they can both receive the address signal sent by the CPU. However, the LDQM /UDQM signals sent to the two memory cells are different, so as to distinguish the high and low bytes of a word.

S3C2440A is a 32-bit CPU, which means that its data bus and address bus width are both 32 bits (it can be understood as 32 wires connected to the CPU at one end and to the memory controller at the other end). Therefore, the input/output end of the memory data must also be a 32-bit bus. MINI2440 uses two 16-bit wide bus memory chips in parallel to form a 32-bit bus. One chip is connected to the lower 16 bits of the CPU data bus, and the other chip is connected to the higher 16 bits of the data bus, which are connected in parallel to form a 32-bit bus. Therefore, the input/output buses of the two chips are connected to different pins on the CPU bus.

1.1.3 SDRAM Read Operation

When SDRAM performs a read operation, the address of the data to be read is first sent to the address line. From the previous knowledge, we know that the address is divided into three parts: row address, column address, and L-Bank chip select signal. The chip select (L-Bank addressing) operation and row valid operation can be performed at the same time.

When CS and L-Bank are addressed, RAS (nSRAS row address strobe signal) is also in a valid state. At this time, the An address line sends the specific row address. A0~A12, there are 13 address lines (can represent 8192 rows), and the different values ​​of A0~A12 determine the specific row address. Since the row is valid, the corresponding L-Bank is also valid, so the row valid can also be called L-Bank valid.

After the row address is determined, the column address needs to be addressed. However, the address lines are still A0~A12 used for the row address. That's right, in SDRAM, the row address and column address lines are multiplexed. The column address reuses A0~A8, a total of 9 (can represent 512 columns). So, how are the read/write commands issued? In fact, there is no signal that sends a clear command to read or write, but the purpose of reading/writing is achieved by controlling the writable state of the chip. Obviously, the WE signal (nWE) is a key. When WE is invalid, it is of course a read command. When it is valid, it is a write command.

SDRAM basic operation commands are completed through a combination of various control/address signals (H represents high level, L represents low level, and X represents high and low levels have no effect). In this table, except for the self-refresh command, all commands are valid by default CKE (SCKEl input clock frequency is valid). The column addressing signal and the read and write commands are issued at the same time. Although the address line is shared with the row addressing, the CAS (nSCAS column address selection signal) signal can distinguish the difference between row and column addressing, and cooperate with A0~A8, A9~A11 to determine the specific column address.

The read command is sent together with the column address (when WE is low, it is a write command). However, when sending the column read and write command, there must be an interval with the row valid command. This interval is defined as tRCD, that is, RAS to CAS Delay. This is easy to understand. After sending the row address on the address line, it is necessary to wait until the row address is stabilized before sending the column address. tRCD is an important timing parameter of SDRAM. For relevant values, refer to the corresponding chip hardware manual. Usually tRCD is in the unit of clock cycles (tCK, Clock Time). For example, the memory chip used by the author's MINI2440 has a tRCD of 20nst. If the memory works at 100MHz in the future, then RCD must be at least 2 clock cycles, RCD=2.

Figure 2-53 SDRAM read operation timing diagram

After selecting the column address, the specific storage unit has been determined. The remaining is to wait for the data to be output to the memory data bus through the data I/O channel (DQ). However, after the column address selection signal CAS is issued, it still takes a certain amount of time for data to be output. The period from the issuance of CAS and the read command to the output of the first data is defined as CL (CAS Latency). Since CL only appears when reading, CL is also called read latency (RL). The unit of CL is the same as tRCD, which is also the number of clock cycles. The specific time consumption is determined by the clock frequency (the author's official manual CL=3). However, CAS is not delivered to the storage unit after the CL cycle. In fact, CAS arrives instantly like RAS. Due to the size of the chip, the capacitance in the storage unit is very small, so the signal must be amplified to ensure its effective recognition. This amplification/driving work is done by S-AMP. But it needs a preparation time to ensure the signal transmission strength. This period of time is called tAC (Access Time from CLK, access time after clock triggering).

1.1.4    SDRAM Precharge Operation

From the structural diagram of the storage body, it can be seen that the capacitor with a logic state of 1 will become a logic 0 due to discharge after the read operation. Since the addressing of SDRAM is exclusive, after completing the read and write operations, if you want to address another row of the same L-Bank, you must close the original operation row and resend the row/column address. When closing the original operation row, in order to maintain the data when closing the current row, DRAM must rewrite the original information in the storage body. This process of charging, rewriting and closing the operation row is called pre-charging. When sending the pre-charge signal, it means that the storage body is charged first, and then the current L-Bank operation row is closed. The rewrite operation in the pre-charge is the same as the refresh operation (described in detail later), except that the pre-charge is not periodic, but only performed after the read operation.

1.1.5    SDRAM Burst Operation

Burst refers to the method of continuous data transmission between adjacent storage cells in the same row. The number of storage cells (columns) involved in the continuous transmission is the burst length (Burst Length, BL for short).

At present, since the memory controller reads/writes data of P-Bank width at a time, that is, 8 bytes, but in reality data less than 8 bytes is rare, it usually takes multiple cycles to transmit data. The read/write operations mentioned above address one storage unit at a time. If you want to read/write continuously, you also need to address the next unit of the current storage unit, that is, you need to continuously send column addresses and read/write commands (row addresses remain unchanged, so there is no need to address the ground). Although the same read/write delay allows data transmission to be continuous at the I/O end, it occupies a large amount of memory control resources, and it is inefficient to enter new commands when data is continuously transmitted. For this reason, a burst transmission mechanism is introduced. As long as the starting column address and burst length are specified, the memory will automatically read/write the data storage units of the corresponding length data in turn without the need for the controller to continuously provide column addresses. In this way, except for the transmission of the first data, which requires several cycles (mainly the delay between them, generally tRCD + CL), each subsequent data only needs one cycle.

To summarize:

The basic read operation of SDRAM requires a series of commands to be issued in coordination with the control line and the address line. First, issue the chip valid command (ACTIVE) and lock the corresponding L-BANK address (given by BA0 and BA1) and row address (given by A0 to A12). After the chip activation command, you must wait for a time greater than tRCD (the delay indicator from RAS to CAS of SDRAM) before issuing a read command. After CL (CAS delay value) clock cycles, the read data appears on the data bus in sequence. At the end of the read operation, a precharge (PRECHARGE) command must be issued to the SDRAM to close the activated L-BANK. After waiting for tRP time (after the PRECHAREG command, the row can be accessed again after tRP time), the next read and write operation can be started. The read operation of SDRAM supports burst mode (Burst Mode), and the burst length is optional for 1, 2, 4, and 8.

1.1.6    SDRAM Write Operation

The basic write operation of SDRAM also requires a series of commands to be issued in coordination with the control line and the address line. First, issue a chip valid command and lock the corresponding L-BANK address (given by BA0 and BA1) and row address (given by A0 to A12). After the chip valid command is issued, it is necessary to wait for a time greater than tRCD before issuing the write command data, and the data to be written is sent to the DQ (data line) in sequence. After the last data is written, delay the tWR time. Issue a precharge command to close the activated page. After waiting for tRP time, the next operation can be carried out. There are two types of write operations: burst write and non-burst write. The burst length is the same as the read operation.

Figure 2-54 SDRAM write operation timing diagram

1.1.7    SDRAM refresh

The reason why SDRAM is called DRAM is that it needs to be constantly refreshed to retain data, so it is the most important operation of SDRAM.

The refresh operation is the same as the rewrite operation in precharge, both use S-AMP to read first and then write. But why do we need to refresh when there is a precharge operation? Because precharge is an operation on the working rows in one or all L-Banks, and it is irregular, while refresh has a fixed cycle and operates on all rows in turn to retain the data in the storage body that has not been rewritten for a long time. But unlike the precharge of all L-Banks, the rows here refer to the rows with the same address in all L-Banks, while the working row addresses in each L-Bank in precharge are not necessarily the same. So how long should the refresh be repeated? The currently recognized standard is that the upper limit of the effective storage period of the data of the capacitor in the storage body is 64ms (milliseconds, 1/1000 seconds), which means that the cycle period of each row refresh is 64ms. So the refresh time interval is: 64m/number of rows s. When we look at memory specifications, we often see the logo of 4096 Refresh Cycles/64ms or 8192 Refresh Cycles/64ms. Here, 4096 and 8192 represent the number of rows in each L-Bank in this chip. The refresh command is valid for one row at a time, and the refresh interval also varies with the total number of rows. When there are 4096 rows, it is 15.625μs (microseconds, 1/1000 milliseconds), and when there are 8192 rows, it is 7.8125μs. There are two types of refresh operations: Auto Refresh, referred to as AR, and Self Refresh, referred to as SR. Regardless of the refresh mode, there is no need to provide row address information externally, because this is an internal automatic operation. For AR, there is a row address generator (also called refresh counter) inside the SDRAM to automatically generate row addresses in sequence. Since the refresh is performed on all storage bodies in a row, there is no need for column addressing, or CAS is valid before RAS. Therefore, AR is also called CBR (CAS Before RAS, column positioning ahead of row) refresh. Since the refresh involves all L-Banks, all L-Banks stop working during the refresh process, and each refresh takes 9 clock cycles (PC133 standard), after which it can enter the normal working state, that is, during these 9 clock periods, all working instructions can only wait and cannot be executed. After 64ms, the same row is refreshed again, and the refresh cycle is repeated over and over again. Obviously, the refresh operation will definitely affect the performance of SDRAM, but this is unavoidable, and it is also the price paid by DRAM to gain cost advantages over SRAM (static memory, which can retain data without refreshing). SR is mainly used to save data in the low-power state of sleep mode. The most famous application in this regard is STR (Suspend to RAM). When the AR command is issued, CKE is set to an invalid state, and the SR mode is entered. At this time, it no longer relies on the system clock to work, but refreshes according to the internal clock. During the SR period, all external signals except CKE are invalid (no external refresh instruction is required). Only by re-enabling CKE can the self-refresh mode be exited and the normal operation state be entered.

SDRAM related registers:

(1) BWSCON register (BUS WIDTH & WAIT CONTROL REGISTER)

Table 2-17 SDRAM Control Register (BWSCON)

According to the memory configuration and chip model of the development board, set the bit width and wait state of each BANK solder chip

BWSCON, each 4 bits corresponds to a BANK, these 4 bits represent:

l STx: Enable/disable SDRAM data mask pin (UB/LB). SDRAM does not have high and low bit mask pins. This bit is 0. SRAM is connected to UB/LB pins and is set to 1.

 Note: The UB/LB data mask pins are used to control the high and low bytes of the chip read/write (compare the wiring diagrams of SDRAM and SRAM in the hardware manual)

l WSx: Whether to use the WAIT signal of the memory, usually set to 0

l DWx: Set the bit width of the soldered memory chip. The author's development board uses two SDRAM chips with a capacity of 32M and a bit width of 16 to form a 64M, 32-bit memory. Therefore, DW7 and DW6 bits are set to 0b10, and other BANKs do not need to be set and can use the default values.

l BANK0 corresponds to the system boot BANK. These 4 bits are special. Their settings are determined by the hardware jumper, so they do not need to be set.

l BWSCON setting result: 0x22000000

(2) BANKCON0~BANKCON5 (BANK CONTROL REGISTER)

Table 2-18 BANKCON0~BANKCON5 control register (BANKCON0~BANKCON5)

These 6 registers are used to set the access timing corresponding to BANK0~BANK5. The default value 0x700 is sufficient.

(3) BANKCON6~BANKCON7 (BANK CONTROL REGISTER)

Table 2-19 BANKCON6~BANKCON7 control register (BANKCON6~BANKCON7)

Since the memory is soldered on these two banks, the memory driver mainly sets these two registers.

l MT: Set the memory type of BANK6~BANK7,

00=ROM or SRAM 01=Reserved

10=Reserved 11=SDRAM

The memory is SDRAM, set to 0b11, the corresponding Trcd and SCAN bits should be set, and the other bits have nothing to do with SDRAM

l Trcd: RAS to CAS Delay row address strobe to column address strobe delay. For this parameter, please refer to the extended explanation of memory working principle. The author's memory chip is HY57V561620. From its chip manual, we know that its Trcd is at least 20ns. If the memory works at 100MHz, the value must be at least 2 clock cycles. It is usually set to 3 clock cycles, so it is set to 0b01

l SCAN: SDRAM Column Address Number SDRAM column address number. The author's memory chip is HY57V561620, the column address number is 9, set to 0b01

l The result of setting BANK6 and BANK7 is: 0x18005

(4) REFRESH (REFRESH CONTROL REGISTER)

Table 2-20 Refresh frequency setting register (REFRESH)

SDRAM refresh is enabled, refresh frequency setting register (refresh)

l REFEN: Enable/disable the refresh function. Set it to 1 to enable the refresh function.

l TREFMD: SDRAM refresh mode, 0=CBR/AutoRefresh, 1=Self Refresh, set to 0, automatic refresh

l Trp: row address strobe precharge time, usually set to 0b00

l Tsrc: Single row refresh time, set to 0b11.

l Refresh Counter: The number of memory storage unit refreshes, which is calculated by the following formula:

Refresh Counter = 2^11 + 1 – SDRAM clock frequency (MHz) * SDRAM refresh cycle (uS)

The refresh cycle of SDRAM, that is, how often the memory storage unit needs to be refreshed. From the analysis of the working principle of memory, we know that the upper limit of capacitor data storage is 64ms. The memory chip I use has 8192 rows per L-Bank, so the maximum interval of each refresh is: 64ms/8192 = 7.8125uS. If the memory works at an external crystal frequency of 12MHz, Refresh Counter = 1955. If the memory works at 100MHz, then Refresh Counter = 1269 (take a large integer)

The REFRESH register is set to:

0x8e0000 + 1269 = 0x008e04f5 (HCLK = 100MHz)

0x8e0000 + 1955 = 0x008e07a3 (HCLK = 12MHz)

(5) BANKSIZE REGISTER

Table 2-21 BANKSIZE register (BANKSIZE)

Set the memory burst mode, power saving mode and memory capacity.

l BURST_EN: Whether to enable burst mode, 0 = ARM core prohibits burst transmission 1 = Enable burst transmission, set to 1 to enable burst transmission

l SCKE_EN: Whether to use the SCKE signal as the power saving mode control signal, 0 = Do not use the SCKE signal as the power saving mode control signal 1 = Use the SCKE signal as the power saving mode control signal, usually set to 1

l SCLK_EN: Set the input frequency to the memory, 0 = always input SCLK frequency, even if there is no memory operation, 1 = input SCLK frequency only when performing memory data operation, usually set to 1

l BK76MAP: Set the memory capacity of Bank6/7. The author uses two 32M memory chips in parallel to form 64M memory on the development board. They are all connected to Bank6, so 0b001 is selected.

l BANKSIZE register is set to: 0xb1

(6) SDRAM mode setting register MRSRx (SDRAM MODE REGISTER SET REGISTER)

Table 2-22 SDRAM mode setting register (MRSRx)

This register is used to set the CAS latency period. The only bit that can be manually set is CL[6:4]. From the previous memory working principle, we know that the author uses the development board CL=3, that is, 0b011

l MRSR6, MRSR7 are set to: 0x00000030

1.1.8 Memory driver experiment

Set the runtime address of the project to 0x30000000 when it is loaded, as shown in Figure 2-55:

Figure 2-55 Setting the runtime address when loading

init.s: This program file mainly realizes turning off the watchdog, initializing the memory, copying the ROM data to the memory, and then jumping to the memory to execute the xmain function. After returning from the xmain function, all LEDs are turned on and an infinite loop is entered.

main.c: This program file mainly implements the initialization of the LED lights, and then the four LED lights are cycled and lit 5 times, and the xmain function returns.

delay.s: This program file is mainly compiled to realize the delay function.

   Memory initialization can also be implemented using the following C program:

C language version:

#define MEM_CTL_BASE 0x48000000

#define MEM_CTL_END 0x48000034

/* Values ​​of 13 SDRAM registers */

unsigned long const mem_cfg_val[]={ //Declare array to store memory controller setting data

           0x22000000, //BWSCON

           0x00000700, //BANKCON0

           0x00000700, //BANKCON1

           0x00000700, //BANKCON2

           0x00000700, //BANKCON3   

           0x00000700, //BANKCON4

           0x00000700, //BANKCON5

           0x00018005, //BANKCON6

           0x00018005, //BANKCON7

           0x008e07a3, //REFRESH (HCLK = 12MHz, the value is 0x008e07a3

                                                //HCLK = 100MHz 0x008e04f5)

           0x000000b1, //BANKSIZE

           0x00000030, //MRSRB6

           0x00000030, //MRSRB7

};

void mem_init(void)

{

         int i = 0;

         unsigned long *p = (unsigned long *)MEM_CTL_BASE;

         for(; i < (MEM_CTL_END - MEM_CTL_BASE)/4; i++)

                    p[i] = mem_cfg_val[i];

}