Abnormal interruption of ARM system

　　 1: During normal execution, the value of the program counter register PC increases by four bytes for each ARM instruction executed, and the value of the program counter register PC increases by two bytes for each Thumb instruction executed. The entire process is executed sequentially.　　

　　 2: Through the jump instruction, the program can jump to the specified address label for execution, or jump to a specific subroutine for execution. The B instruction is used to perform the jump operation, and the BL instruction is used to save the corresponding return address of the subroutine while performing the jump operation. BX separates the lowest bit of the target address while performing the jump operation, and can switch the program to THumb state. BLX performs the above three operations

　　 3: When an abnormal interrupt occurs, the system will execute the current instruction and then jump to the corresponding abnormal interrupt handler for execution. After the abnormal interrupt handler is executed, the program returns to the next instruction where the interrupt occurred to continue execution. When entering the abnormal interrupt handler, the execution scene of the interrupted program must be saved. When exiting from the abnormal interrupt program, the execution scene of the interrupted program must be restored.

ARM processor's response to abnormal interrupt

　　1 Save the current state of the processor, the interrupt mask bit, and each condition flag bit. This is achieved by saving the contents of the current program status register CPSR to the SPSR register corresponding to the exception interrupt to be confident.

　　2 Set the corresponding bits of the current program status register, including the bits in the CPSR, so that the processor enters the corresponding execution mode, sets the bits in the CPSR, and the IRQ interrupt is executed, but when entering the FIQ, the FIQ interrupt is executed.

　　3 Set the register to the return address

　　4 Set the program counter PC to the interrupt vector address of the long exception interrupt, so as to jump to the corresponding exception interrupt for processing

Return from exception handling

　　1 Restore the processor status of the interrupted program and transfer the contents of the SPSR_mode register to the CPSR

　　2 Return to the next instruction of the instruction where the abnormal interrupt occurred, and write the content in IR_MODE to PC

　　3 Reset and exception interrupt do not need to return, the different exception interrupts pointed to by the program counter PC are different