S3C2440 system interrupt

1.1 S3C2440 system interrupt

The CPU and peripherals constitute a computer system. The CPU and peripherals are connected through a bus for data communication and control. The CPU manages and monitors all hardware in the computer system. There are usually two ways to manage and monitor the hardware:
l Query mode: The CPU keeps querying the current status of each hardware and decides whether to process it based on the hardware status. It is like an inspector in a factory, constantly checking the working status of each position and handling it in time when it finds a situation. This method is simple to implement and is usually used in systems with only a small amount of peripheral hardware. If a computer system has a lot of hardware, this method is undoubtedly time-consuming and inefficient. It also occupies a lot of CPU resources and is slow to respond to multi-tasking systems.
l Interrupt mode: When a hardware generates an event that needs to be processed by the CPU, it actively "notifies" the CPU through a signal line and sets the corresponding bit in a register. Once the CPU finds that the level on this signal line has changed, it will interrupt the current program and then process the interrupt request. This is like a critical care ward in a hospital. There is an emergency button at the head of each bed in the ward. The button is connected to an indicator light on the console in the ward monitoring room. As long as an emergency occurs in the bed, the patient presses the button, and the bell in the ward monitoring room will ring to notify the medical staff of the emergency. The medical staff will then check the indicator light on the console to find the specific ward and bed number and go directly to deal with the emergency. The interrupt processing method is much more complicated than the query method and requires hardware support, but it has higher real-time processing performance. This method is basically used in embedded systems.
System interrupts are a mechanism for embedded hardware to process internal or external events in real time. For different CPUs, the processing of interrupts is different only in details, and the general processing flow is the same. The interrupt controller structure of S3C2440A is shown in the figure below:

 
Figure 3-3 S3C2440 interrupt controller
The interrupt request is generated by hardware. According to the interrupt source type, the interrupt signal is sent to the SUBSRCPND (SubSourcePending) and SRCPND (SourcePending) registers. SUBSRCPND is a sub-interrupt source temporary register, which is used to save the sub-interrupt source signal. SRCPND is an interrupt source temporary register, which is used to save the interrupt source signal. The interrupt signal can be masked by programming. SUBMASK is a sub-interrupt source mask register, which can mask the specified sub-interrupt signal. The MASK function is the same as SUBMASK and is used to mask the interrupt source signal. Interrupts are divided into two modes: general interrupts and fast interrupts. MODE is an interrupt mode judgment register, which is used to judge whether the current interrupt is a fast interrupt. If it is a fast interrupt, the fast interrupt signal is directly sent to the ARM core. If it is not a fast interrupt, the interrupt signal must be arbitrated. S3C2440A supports up to 60 interrupts. It is very likely that multiple hardware will generate interrupt requests at the same time. At this time, the interrupt controller is required to make a decision. Priority is the interrupt source priority arbitration selector. When multiple interrupts are generated, the interrupt source with the highest priority is selected for processing. INTPND is the interrupt source result register, which stores the only interrupt source arbitrated by the priority.
1 Interrupt Generation - Interrupt Source

S3C2440A supports 60 interrupt sources, which basically meets the interrupt requirements of the development board, external devices, etc. Each interrupt source corresponds to one bit in the register. Obviously, at least two 32-bit registers are required to support 60 interrupts. SUBSRCPND and SRCPND respectively store the interrupt source signals. S3C2440A manages 60 interrupt sources in a hierarchical manner. As shown in Figure 3-4:


 
Figure 3-4 Schematic diagram of interrupt source signal compound
S3C2440A divides interrupt sources into two levels: interrupt source and sub-interrupt source. The interrupt source contains a single interrupt source and a composite interrupt source. The composite interrupt source is a composite signal of the sub-interrupt source. For example, the real-time clock interrupt, the hardware will only generate one interrupt, which is a single interrupt source, and its interrupt signal line is directly connected to the interrupt source register. For the composite interrupt source, take the UART serial port as an example. S3C2440A can support 3 UART serial ports, each serial port corresponds to a composite interrupt source signal INT_UARTn, and each serial port can generate three interrupts, that is, three sub-interrupts: receive data interrupt INT_RXDn, send data interrupt INT_TXDn, data error interrupt INT_ERRn. These three sub-interrupt signals are combined into one interrupt signal in the interrupt source register. Any of the three interrupts will pass the interrupt signal to the corresponding interrupt source INT_UARTn, and then pass it to the ARM core through the interrupt signal line.


 
Figure 3-5 Schematic diagram of the composite UART serial port interrupt source signal
Total interrupt source details The following table lists some interrupt sources of S3C2440A, which correspond to a certain bit in the interrupt source register: For detailed interrupt sources, please refer to the S3C2440A hardware manual.
Table 3-5 Some interrupt source signals

Interrupt Sources	describe	Priority Arbitration Group
INT_ADC	Digital-to-analog conversion and touch screen interrupt	ARB5
INT_RTC	Real-time clock interrupt	ARB5
INT_UART0	UART0 interrupt (including sub-interrupts)	ARB5
INT_NFCON	NandFlash control interrupt	ARB4
INT_WDT_AC97	Watchdog interrupt	ARB1
EINT8-23	External interrupts 8~23 (including external sub-interrupts)	ARB1
EINT4-7	External interrupts 4 to 7 (including external sub-interrupts)	ARB1
EINT3	External interrupt 3	ARB0
EINT2	External interrupt 2	ARB0
EINT1	External interrupt 1	ARB0
EINT 0	External interrupt 0	ARB0

In addition to the above classification, interrupt signals can also be divided into external interrupt sources and internal interrupt sources according to the hardware location.
l Internal interrupt source: It is an interrupt signal generated by common hardware in embedded systems, such as: UART serial port interrupt source, clock Timer interrupt source, watchdog interrupt source, etc.
l External interrupt source: Sometimes embedded systems need to mount some external devices on the external interface. These devices are not essential hardware in a general embedded system, such as: Bluetooth modules, various sensors, WIFI wireless communication modules, these hardware also need to generate interrupts to allow the CPU to process data, so these peripheral hardware are connected to the interrupt controller through interrupt signal lines, and the interrupts they generate are called external interrupt signals. They have the same processing mechanism as internal interrupts, but it does not have a fixed interrupt number corresponding to it. The connection between hardware and embedded systems and interrupt processing are completely implemented by system hardware and software designers.
The peripheral hardware is connected to the embedded system through the input and output interface I/O Ports. The I/O Ports provide the peripherals with external interrupt signal lines, output power, frequency clock and input and output signal lines. The external hardware is connected to the I/O Ports according to its own needs. When an interrupt occurs, the interrupt signal is sent to the external interrupt signal line, and then transmitted to the interrupt controller through the external interrupt signal line.
The key Key can be considered as the simplest hardware device, as shown in the following figure:


 
Figure 3-6 Schematic diagram of key hardware wiring
Its function is very simple. It can connect the circuit. One end of the key K1~K6 is grounded as a low level, and the other end is connected to the positive pole of the power supply as a high level. The six interrupt signal lines EINT8, EINT11, EINT13, EINT14, EINT15, and EINT19 are connected to the high-level end of the key respectively. When the key is pressed, the circuit is connected, the entire circuit becomes a low level, and the voltage on the interrupt signal line changes. By setting the interrupt trigger mode, an external interrupt request is generated and input into the CPU, thereby realizing key interrupt control.
S3C2440A can support 24 types of external interrupts from EINT0 to EINT23, which can fully meet the needs of peripheral hardware of small embedded devices.
External interrupt sources are also divided into external interrupt sources and external sub-interrupt sources, and their processing methods are basically the same as internal interrupt sources.
 

1.1.1 Interrupt Priority

S3C2440A supports 60 interrupts. Multiple hardware may generate interrupt requests at the same time. Since the CPU can only handle one interrupt, how does the interrupt controller select the best interrupt and hand it over to the ARM core for processing? The interrupt controller uses priority arbitration comparison to select and find the interrupt source with the highest priority. The interrupt controller divides the 60 interrupt sources into 7 groups, as shown in the figure below. It is similar to the competition method in sports events. All contestants compete in the group stage, select the best player in the group stage, and then enter the final stage to compete with the top priority of other groups. The final winner is the champion. ARBITER0~ARBITER5 is the "group stage". The interrupt source signal performs priority arbitration in each group and selects the highest priority interrupt signal. The interrupt signal selected by each group is sent to ARBITER6, which is the final stage. The highest priority interrupt signal is selected and handed over to the ARM core.

 
Figure 3-7 S3C2440 priority arbitration diagram
The priority of the interrupt signal when competing in the 7 groups is programmable, and the priority is set through the PRIORITY register. As shown in the following table (only some bits of the PRIORITY register are listed):
Table 3-6 Interrupt priority control register (PRIORITY)

Register Name	address	Read and write	describe	Reset Defaults
PRIORITY	0x4A00000C	R/W	Interrupt Priority Control Register	0x7F

 

PRIORITY	Bit	describe	Initial Value
ARB_SEL6	[20:19]	Arbitration Group 6 Priority Sorting 00 = REQ 0-1-2-3-4-5  01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5  11 = REQ 0-4-1-2-3-5	0x00
ARB_SEL5	[18:17]	Arbitration Group 5 Priority Order 00 = REQ 1-2-3-4 01 = REQ 2-3-4-1 10 = REQ 3-4-1-2 11 = REQ 4-1-2-3	00
…	…	…	…
ARB_MODE6	[6]	Whether the priority of arbitration group 6 rotates: 0 = no rotation, 1 = rotation	1
ARB_MODE5	[5]	Whether the priority of arbitration group 5 rotates: 0 = no rotation, 1 = rotation	1
…	…	…	…

By setting the priority sorting mode bit of arbitration group n, the priority order of the interrupt signal in each arbitration group is set. For example, when ARB_SEL5 is grouped, it contains four interrupt signals: REQ1 INT_UART0, REQ2 INT_SPI1, REQ3 INT_RTC, REQ4 INT_ADC. The ARB_SEL5 bit uses the default value: 00. When the INT_UART0 and INT_RTC interrupt signals are generated at the same time, INT_UART0 will be selected. The priority of the interrupt signal can be changed by changing the priority sorting mode in a programmable way.
ARB_MODE0~ARB_MODE6 is the priority rotation setting bit for each arbitration group. When the default value is used, after the current interrupt signal is selected for processing, when an interrupt request is generated again, its priority automatically rotates to the lowest in the group. This ensures that the interrupt signal with a low priority can be processed in time, so that the interrupt with a high priority and frequent interrupt requests will not be processed first every time, while the interrupt with a low priority will be "starved to death". Obviously, this method is more democratic and has better real-time performance.

2 Interrupt controller related registers

(1) SUBSRCPND sub-interrupt source temporary register
Table 3-7 Sub-interrupt source temporary register (SUBSRCPND)

Register Name	address	Read and write	describe	Reset Defaults
SUBSRCPND	0x4A000018	R/W	Sub-interrupt source temporary register, saves interrupt request status: 0: No interrupt request signal 1: Interrupt request signal generated	0x00000000

 

SUBSRCPND	Corresponding to SRCPND	Bit	describe	Initial Value
Reserved	none	[31:15]	Unused	0
INT_AC97	INT_WDT_AC97	[14]	0 = No interrupt is generated 1 = Interrupt is generated	0
…	…	…	…	…
INT_RXD0	INT_UART0	[0]	0 = No interrupt is generated 1 = Interrupt is generated	0

This register is used to identify and save the sub-interrupt source signal. When a sub-interrupt signal is generated, the corresponding bit of SUBSRCPND is automatically set to 1. This bit will remain set until the interrupt handler clears it. It should be noted that clearing the interrupt is done by writing 1 to the corresponding bit, not 0. Writing 0 is invalid.
(2) INTSUBMSK sub-interrupt source mask register
Table 3-8 Sub-interrupt source mask register (INTSUBMSK)

Register Name	address	Read and write	describe	Reset Defaults
INTSUBMSK	0x4A00001C	R/W	Sub-interrupt source signal mask storage register, set the corresponding bit to mask the interrupt signal: 0: Unmasked, interrupt is available 1: Mask the interrupt signal	0xFFFF

 

INTSUBMSK	Bit	describe	Initial Value
Reserved	[31:15]	Unused	0
INT_AC97	[14]	0 = Unmasked 1 = Interrupt masked	1
…	…	…	…
INT_RXD0	[0]	0 = Unmasked 1 = Interrupt masked	1

This register is used to mask the sub-interrupt source signal. The default value is that all sub-interrupts are masked. Therefore, if you want to process a hardware interrupt, you must turn on the interrupt mask bit and write 0 to unmask the interrupt.
(3) SRCPND interrupt source temporary register
Table 3-9 Interrupt source temporary register (SRCPND)

Register Name	address	Read and write	describe	Reset Defaults
SRCPND	0x4A000000	R/W	Interrupt source temporary register, save the interrupt request status: 0: No interrupt request signal 1: Interrupt request signal generated	0x00000000

 

SRCPND	Bit	describe	Initial Value
INT_ADC	[31]	0 = No interrupt is generated 1 = Interrupt is generated	0
…	…	…	…
EINT0	[0]	0 = No interrupt is generated 1 = Interrupt is generated	0

This register is used to save the interrupt source signal. When an interrupt signal is generated, the corresponding bit of SRCPND is automatically set to 1. This bit will remain set until the interrupt handler clears it. Please note that the interrupt is cleared by writing 1 to the corresponding bit, not 0. Writing 0 is invalid.
(4) INTMSK interrupt source mask register
Table 3-10 Interrupt source mask register (INTMSK)

Register Name	address	Read and write	describe	Reset Defaults
INTMSK	0x4A000008	R/W	Interrupt source signal mask storage register, set the corresponding bit to mask the interrupt signal: 0: Unmasked, interrupt is available 1: Mask the interrupt signal	0xFFFFFFFF

 

INTMSK	Bit	describe	Initial Value
INT_ADC	[31]	0 = Unmasked 1 = Interrupt masked	1
…	…	…	…
EINT0	[0]	0 = Unmasked 1 = Interrupt masked	1

This register is used to mask the interrupt source signal. The default value is that all interrupts are masked. Therefore, if you want to process a hardware interrupt, you must turn on the interrupt mask bit and write 0 to unmask the interrupt.
(5) INTPND highest priority interrupt temporary register
Table 3-11 Highest priority interrupt temporary register (INTPND)

Register Name	address	Read and write	describe	Reset Defaults
INTPND	0x4A000010	R/W	The highest priority interrupt temporary register stores the result of priority arbitration: 0: No interrupt request signal 1: Interrupt request signal generated	0x00000000

 

INTPND	Bit	describe	Initial Value
INT_ADC	[31]	0 = No interrupt is generated 1 = Interrupt is generated	0
…	…	…	…
EINT0	[0]	0 = No interrupt is generated 1 = Interrupt is generated	0

This register stores the interrupt signal bit obtained through priority arbitration. It is the interrupt with the highest priority among all current interrupt requests. Therefore, at most one bit in this register is set to 1. Usually, the interrupt handler will read the value of this register to obtain the interrupt request currently being processed. After the interrupt processing is completed, the interrupt is cleared by writing 1.
(6) INTOFFSET interrupt number offset register
Table 3-12 Interrupt number offset register (INTOFFSET)

Register Name	address	Read and write	describe	Reset Defaults
INTOFFSET	0x4A000014	R	Interrupt number offset register, used to save the interrupt number currently being processed	0x0000000

This register stores the interrupt number corresponding to the interrupt signal that has been arbitrated by priority. It is an integer between 0 and 31. In fact, it is the corresponding bit number in INTPND. For example, INT_UART0 generates an interrupt, the 28th bit in INTPND is set to 1, and the integer stored in INTOFFSET is 28. The purpose of this register is mainly to facilitate the interrupt handler to query the interrupt source and clear the interrupt source:

#define TIMER0_IRQ_OFT 10 // Clock 0 timing interrupt
#define EINT0_IRQ_OFT 0 // Development board K1 button 1 corresponds to external interrupt EINT0
void handle_irq()
{
    unsigned long irqOffSet = INTOFFSET; // Get the interrupt number
    switch(irqOffSet)
    {
                  case TIMER0_IRQ_OFT: // The current interrupt is the timer 0 interrupt
                    do_timer(); // Jump into the timer 0 handler
                        break;
                  case EINT0_IRQ_OFT: // The current interrupt is triggered by the K1 button
                       do_key1_pressed(); // Process the K1 press event
                        break;
    }
   
    SRCPND &= (1<     INTPND = INTPND; // Clear the highest priority interrupt register interrupt
}
 
(7) INTMOD interrupt mode register
Table 3-13 Interrupt mode register (INTMOD)

Register Name	address	Read and write	describe	Reset Defaults
INTMOD	0x4A000004	R/W	Interrupt mode register, specifies the corresponding interrupt mode: 0 = IRQ general interrupt mode 1 = FIQ fast interrupt mode	0x0000000

 

INTMOD	Bit	describe	Initial Value
INT_ADC	[31]	0 = IRQ 1 = FIQ	0
…	…	…	…
EINT0	[0]	0 = IRQ 1 = FIQ	0

Generate an interrupt by setting the ARM core. It should be noted that there is no priority arbitration for fast interrupts, and only one bit can be set to FIQ mode.