Pin description and off-chip bus structure of stc-52 single-chip microcomputer

    RST reset (high level reset): When the input signal is high level for more than 2 machine cycles, it is valid and is used to complete the reset initialization operation of the microcontroller. It is recommended to connect a pull-down resistor of about 8.2k between this pin and the VSS pin, and a capacitor of about 10μF between this pin and the VCC pin to ensure reliable reset.

    VPD backup power supply: During VCC power failure, this pin can be connected to the backup power supply to ensure that the data in the internal RAM is not lost. When the VCC main power supply drops below the specified level and VPD is within its specified voltage range (5±0.5V), VPD provides backup power to the internal RAM.

18, 19, clock pin

    The clock pin is connected to an external crystal and the inverting amplifier on the chip to form an oscillator, which provides the clock control signal of the microcontroller. The clock pin can also be connected to an external crystal oscillator.

(1) XTAL1 (pin 19): A pin connected to an external crystal. Inside the microcontroller, it is the input of the inverting amplifier. This amplifier forms the on-chip oscillator. If an external crystal oscillator is used, this pin should be grounded.

(2) XTAL2 (pin 18): Connected to the other end of the external crystal, and connected to the output of the internal inverting amplifier inside the microcontroller. If an external crystal oscillator is used, this pin receives the oscillator signal, that is, directly connects this signal to the input of the internal clock generator.

   XTAL1 and XTAL2 are often connected to a feedback loop consisting of a quartz crystal oscillator and capacitors to output rectangular pulses as the clock signal of the microcontroller.

29. PSEN (pin 29)

    Read select signal of external program memory. When executing MOVC to access the off-chip program, PSEN automatically generates a low level to implement the read operation of the external ROM unit, and it is a high level in other cases.

1. When the internal ROM is read, PSEN does not work;

2. When reading from external ROM, it will act twice in each machine cycle. However, during this period, whenever the external data memory is accessed, these two valid PSEN signals will not appear;

3. When reading from external RAM, two PSEN pulses are skipped and will not be output;

4. When connecting to an external ROM, connect it to the OE pin of the ROM.

30, ALE/PROG (pin 30)

    The first function ALE (Address Lock Enable) is address latch enable, which is used when accessing off-chip memory. When the system is expanded, ALE is used to control the output of the low 8-bit address of port P0 to be sent to the latch for latching, so as to achieve the isolation of low-order address and data. When 8051 expands external ROM, ALE is connected to the G terminal of the 74LS373 latch. When the CPU accesses the outside, it is used to lock the low-order address of the address, that is, the output of port P0.

    Since ALE is a positive pulse output at a fixed frequency of one sixth of the crystal oscillator, when the external memory is not used in the system, the ALE pin will also have a fixed frequency output of one sixth, so it can be used as an external clock or external timing pulse. It should be noted that whenever the external data memory is accessed, an ALE pulse will be skipped. The ALE terminal can drive (absorb or output current) 8 LS-type TTL input circuits.

    PROG is the second function of this pin and is the programming pulse input terminal.

31, EA/VPP (pin 31)

    EA (Enable Address) is the control terminal for selecting internal and external program memory.

    EA=1, access the on-chip program memory, but when the value of PC (program counter) exceeds 0FFFH (for 8051, 8751), that is, when it exceeds the 4K byte address range of the on-chip program memory, it will automatically switch to executing the program in the external program memory.

    EA=0, the microcontroller only accesses the external program memory. For the commonly used 8031, there is no internal program memory, so the EA pin must be grounded so that only the external program memory can be selected.

    VPP (Voltage Pulse of Programing) is the second function of this pin. It is used to apply programming voltage, such as +21V (8751). For 89C51, the programming voltage applied to the VPP pin is +12V or +5V.

Input/output (I/O) pins P0, P1, P2, P3 (32 in total)

1. P0 port (pin 39 to pin 32): It is a bidirectional 8-bit three-state I/O port. When connected to an external memory, it is multiplexed with the lower 8 bits of the address bus and the data bus, and can drive 8 LS-type TTL loads by absorbing current.

2. P1 port (pin 1 to pin 8): It is a quasi-bidirectional 8-bit I/O port. Since this interface output does not have a high-impedance state and the input cannot be latched, it is not a true bidirectional I/O port. P1 port can drive (absorb or output current) 4 LS-type TTL loads. For 8052 and 8032, the second function of the P1.0 pin is the external input of the T2 timer/counter, and the second function of the P1.1 pin is the T2EX capture and reload trigger, that is, the external control terminal of T2. When programming and verifying the EPROM, it receives the lower 8-bit address.

3. Port P2 (pins 21 to 28): It is a quasi-bidirectional 8-bit I/O port. When accessing external memory, it can be used as the high 8-bit address bus of the expansion circuit to send out the high 8-bit address. During EPROM programming and program verification, it receives the high 8-bit address. P2 can drive (absorb or output current) 4 LS-type TTL loads.

4. P3 port (pins 10 to 17): It is a quasi-bidirectional 8-bit I/O port. In MCS-51, these 8 pins are also used for special functions and are multiplexed dual-function ports. P3 can drive (absorb or output current) 4 LS-type TTL loads.

When used as the first function, it is used as a normal I/O port, and its functions and operation methods are the same as those of the P1 port.

When used as the second function, the definition of each pin is shown in the table.

    It is worth emphasizing that each pin of the P3 port can be independently defined as the input/output of the first function or the second function.

Table P3 Second function definition of each port line

Port pin second function

P3.0 10 RXD (serial input port)

P3.1 11 TXD (serial output port)

P3.2 12 INT0 (external interrupt 0)

P3.3 13 INT1 (external interrupt 1)

P3.4 14 T0 (Timer 0 external input)

P3.5 15 T1 (Timer 1 external input)

P3.6 16 WR (external data memory write pulse)

P3.7 17 RD (external data memory read pulse)

The conditions for making each line of P3 terminal in the second function

1. Serial I/O is in operation (RXD, TXD);

2. Enable the external interrupts (INT0, INT1);

3. The timer/counter is in external counting state (T0, T1);

4. Execute the instructions for reading and writing external RAM (RD, WR).

    In the application, if the second function of each bit of the P3 port is not set (the generation of WR and RD signals does not need to be set), the P3 port line is automatically in the first function state, that is, the working state of the static I/O port. In more cases, according to the needs of the application, several port lines are set to the second function, while the other port lines are in the first function operation state. In this case, it is not appropriate to perform byte operations on the P3 port, and bit operations must be used.
　

Port load capacity

    The P0 port can drive 8 LSTTL loads. If you need to increase the load capacity, you can add a bus driver to the P0 bus. The P1, P2, and P3 ports can each drive 4 LSTTL loads.