Introduction to 51 single chip microcomputer - timer and counter

   8051 has two 16-bit timer/counters T0 and T1, and 8052 has a third timer/counter T2, which can be set as internal timer and external counter through internal programming.
   1. Mode register TMOD
   Special function register TMOD is the working mode register of TO and T1, and its format is as follows:
   The lower four bits of TMOD are the T0 mode field, and the upper four bits are the T1 mode field. When reset, all bits of TMOD are set to 0.
   (1) Working mode selection bits M1 and M0
   The timer/counter has four working modes, which are determined by the values ​​of M1 and M0. The corresponding relationship is as shown in the figure below:
    (2) Mode selection bit C/T
     C/T=0 is timer mode, with fosc (crystal frequency) divided by 12 as the counting signal, that is, the timer increases by 1 in each machine cycle.
     C/T=1 is counter mode, with the pulse input from the external pin (T0 is P3.4, T1 is P3.5) as the input signal, and increases by 1 when the external signal has a negative transition. The maximum frequency of external event counting is 1/24 of fosc.
    (3) Gate bit GATE
     When GATE=1, the timer is started by the external interrupt pins INT0, INT1 and the internal TR0, TR1 bits. When INT0 is high and TR0 is set, timer T0 is started. Timer T1 is started in the same way as T0.
     When GATE=0, timers T0 and T1 are started only by setting TR0 and TR1.
     2. Control register TCON
     The high 4 bits of the special function register TCON store the timer's operation control and overflow flag, and the low 4 bits store the external interrupt trigger mode control bits and latch the external interrupt request source. The format of TCON is as follows:
     (1) The operation control bit TR0 of timer T0
      TR0 is set or cleared by software. When the gate bit GATE=0, the TO counter is controlled only by TR0. When TR0=1, the counting starts, and when TR0=0, it stops. When the gate bit GATE=1, the T0 counter is controlled by INT0 and TR0. When INT0=1 and TR0=1, the T0 counter starts.
      (2) The overflow flag bit TF0 of timer T0
      When T0 overflows, TF0=1, and an interrupt is requested to the CPU. After the CPU responds to the interrupt, TF0 is cleared to 0 by hardware, or TF0 can be cleared to 0 by software query.
      (3) The operation control bit TR1 of timer T1
      has the same function as TR0.
      (4) The overflow flag of timer T1 is TF1, which
      has the same function as TF1.
      (5) Interrupt request flag IE1 of external interrupt source 1 (INT1, P3.3)
      When IE1=1, external interrupt source 1 is requesting an interrupt to the CPU. When the CPU responds to the interrupt, IE1 is cleared to 0 by hardware (falling edge trigger mode).
      (6) External interrupt source 1 trigger mode selection bit IT1
      When IT1=0, external interrupt source 1 selects the level trigger mode, and IE1 is set when the input is low level; when IT1=1, external interrupt source 1 selects the falling edge trigger mode, and IE1 is set when the interrupt source changes from high level to low level, requesting an interrupt to the CPU.
      (7) External interrupt source 0 (INT0, P3.2) interrupt request flag IE0
      has the same function as IE1.
      (8) External interrupt source 0 trigger mode selection bit IT0 has
      the same function as IT1.
      3. Timer working mode
      As mentioned above, the timer has 4 working modes, which are determined by the two bits M1 and M0 in the TMOD register. Note: Only T0 has working mode 3.
     (1) Working mode 0
     When M1 and M0 in the TMOD register are 00, the timer works in mode 0. The following figure uses timer T1 as an example:
     When counting, the lower 5 bits of TL1 overflow and carry to TH1. After TH1 overflows, TF1 is set and an interrupt request is sent to the CPU. Note: In mode 0, TL1 only uses the lower 5 bits, and the upper 3 bits are uncertain and cannot be used. The control logic count enable/disable does not change the count value.
     (2) Working mode 1
     When the values ​​of M1 and M0 in the TMOD register are 01, the timer works in mode 1. The only difference between working mode 1 and working mode 0 is that working mode 1 can achieve 16-bit counting, and the rest is the same as working mode 0. If we take timer T1 as an example to illustrate the diagram, it can be as follows:
       (3) Working mode 2
      When the M1 and M0 bits of the TMOD register are 10, the timer works in working mode 2. Mode 2 is an 8-bit counter that automatically restores the initial value. TL1 is used as an 8-bit counting register and TH1 is used as an 8-bit counting constant register. When TL1 overflows, on the one hand, TF1 is set and an interrupt request is sent to the CPU. On the other hand, the constant preset in TH1 is reloaded into TL1 to continue counting. Reloading will not affect the content of TH1. Its structural diagram is as follows:
   In mode 2, the number of counts can be changed by changing the value of TH1.
   (4) Mode 3
   Mode 3 is only applicable to T0, at which time T1 stops counting.
    4. Calculation of the overflow rate of the timer/counter
    The timer/counter must be set to the initial counting value Ta before working. The initial counting formula is as follows:
   After a given time t, the formula for finding the initial value is as follows:
   5. Summary
   The steps for programming the timer/counter are as follows:
   a. Write TMOD to set the working mode, timing/counting mode, and which timer to start (turn on the corresponding gate bit GATE);
   b. Write the initial value to the corresponding register;
   c. Disconnect or turn off the timer;
   d. Start the timer, that is, write data to TCON.