MSP430 system clock ACLK, MCLK, SMCLK

The MSP430 basic clock module contains the following three clock input sources.
1. 4 clock oscillator sources
   1. LFXT1CLK:   external crystal or clock 1  low-frequency clock source  Low-frequency mode: 32768Hz  High-frequency mode: (400KHz-16MHz)
   2. XT2CLK:     external crystal or clock 2  high-frequency clock source (400KHz-16MHz)
   3. DCOCLK:     internal digital RC oscillator, reset value 1.1MHz
   4. VLOCLK:     internal low-power oscillator  12KHz
   Note: MSP430x20xx:  LFXT1  does not support  HF  mode,  XT2  does not support,  ROSC  does not support.
  
  (1) LFXT1CLK low-frequency clock source: generated by the LFXT1 oscillator (as shown in Figure 2). After resetting OSCOff in the status register by software, LFXT1 starts working, that is, the system uses low-frequency operation. If LFXT1CLK is not used as SMCLK or MCLK signal, OSCOff can be set by software to disable LFXT1 from working.
 
  (2) XT2CLK high-frequency clock source: generated by the XT2 oscillator. It generates the clock signal XT2CLK, and its operating characteristics are similar to those of the LFXT1 oscillator when it works in high-frequency mode. The XT2 oscillator can be simply set to work or
  not through software. When XT2CLK is not used as the SMCLK or MCLK signal, XT2 is turned off and other clock sources are selected. 3) DCOCLK digitally controlled RC oscillator. Generated by the DCO oscillator integrated in the clock module. The DCO oscillator is an RC oscillator, and its frequency can be adjusted by software. Its control logic is shown in Figure 3. When the oscillators LFXT1 and XT2 are disabled or fail, the DCO oscillator is automatically selected as the clock source of MCLK. Therefore, the system interrupt request caused by the failure of the oscillator can be responded to, even when the CPU is turned off.
 
 
   The basic clock module can provide the three clock signals required by the system, namely: ACLK, MCLK, and SMCLK. Among them, the auxiliary clock ACLK is obtained by dividing the LFXT1CLK signal by 1, 2, 4, or 8. ACLK can be selected by software as the clock signal of each peripheral module, and is generally used for low-speed peripherals; the system master clock MCLK can be selected by software from one of LFXT1CLK, XT2CLK, and DCOCLK, and then divided by 1, 2, 4, or 8. MCLK is mainly used for CPU and system. The subsystem clock SMCLK can be selected by software from LFXT1CLK and DCOCLK, or XT2CLK and DCOCLK, and then divided by 1, 2, 4, or 8, and is mainly used for high-speed peripheral modules.