STM32 study notes RCC-EEWORLD

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clock

Three different clock sources can be used to drive the system clock (SYSCLK):

● HSI oscillator clock

● HSE oscillator clock

● PLL clock These devices have the following two secondary clock sources:

● 40kHz low speed internal RC, can be used to drive independent watchdog and RTC through program selection. RTC is used to automatically wake up the system from stop/standby mode.

● A 32.768kHz low speed external crystal can also be used to drive the RTC (RTCCLK) through program selection. When not in use, either clock source can be independently enabled or disabled, thereby optimizing system power consumption.

1. When HSI is used as the PLL clock input, the maximum frequency of the system clock is 64MHz.

2. For the characteristics of internal and external clock sources, please refer to the "Electrical Characteristics" section in the corresponding product data sheet. Users can configure the frequencies of the AHB, high-speed APB (APB2), and low-speed APB (APB1) domains through multiple prescalers. The maximum frequency of the AHB and APB2 domains is 72MHz. The maximum allowed frequency of the APB1 domain is 36MHz. The clock frequency of the SDIO interface is fixed to HCLK/2.

RCC uses the AHB clock (HCLK) divided by 8 as the external clock of the Cortex system timer (SysTick). By setting the SysTick control and status register, the above clock or the Cortex (HCLK) clock can be selected as the SysTick clock. The ADC clock is obtained by dividing the high-speed APB2 clock by 2, 4, 6 or 8.

The timer clock frequency distribution is automatically set by hardware according to the following two situations: 1. If the corresponding APB pre-scaling factor is 1, the timer clock frequency is consistent with the APB bus frequency. 2. Otherwise, the timer clock frequency is set to twice the APB bus frequency connected to it.

void RCC_Configuration(void)

{

SystemInit();

RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | USARTz_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);

#ifndef USE_STM3210C_EVAL

RCC_APB2PeriphClockCmd(USARTy_CLK, ENABLE);

#else

RCC_APB1PeriphClockCmd(USARTy_CLK, ENABLE);

#endif

RCC_APB1PeriphClockCmd(USARTz_CLK, ENABLE);

}

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