Detailed explanation of STM32 clock-EEWORLD

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In STM32, there are five clock sources, HSI, HSE, LSI, LSE, and PLL. In fact, there are four clock sources, as shown in the figure below (gray-blue). PLL is a phase-locked loop circuit that multiplies the frequency.

Get the PLL clock.

①. HSI is the high-speed internal clock, RC oscillator, with a frequency of 8MHz.

②. HSE is a high-speed external clock that can be connected to a quartz/ceramic resonator or an external clock source with a frequency range of 4MHz~16MHz.

③. LSI is a low-speed internal clock, RC oscillator, with a frequency of 40kHz.

④. LSE is a low-speed external clock connected to a quartz crystal with a frequency of 32.768kHz.

⑤、PLL is a phase-locked loop frequency multiplication output, and its clock input source can be selected as HSI/2, HSE or HSE/2. The frequency multiplication can be selected as 2~16 times, but its maximum output frequency shall not exceed

Over 72MHz.

The 40kHz LSI is used by the independent watchdog IWDG. It can also be selected as the clock source of the real-time clock RTC.

LSE, or HSE divided by 128. The clock source of RTC is selected by RTCSEL[1:0].

The STM32 has a full-speed USB module, and its serial interface engine requires a 48MHz clock source. This clock source can only be obtained from the PLL output.

Select 1.5 division or 1 division, that is, when the USB module needs to be used, the PLL must be enabled and the clock frequency must be configured as 48MHz or 72MHz.

In addition, STM32 can also select a clock signal to output to the MCO pin (PA8), which can be selected as the 2-division output of the PLL, HSI, HSE, or system clock.

The system clock SYSCLK is the clock source for most components in the STM32. The system clock can be selected as PLL output, HSI or HSE. The maximum frequency of the system clock

The AHB divider can select 1, 2, 4, 8, 16, 64, 128, 256, or 512 divisions.

The output clock is sent to 5 major modules:

①. HCLK clock sent to AHB bus, core, memory and DMA.

②. The system timer clock is sent to Cortex after being divided by 8.

③. Send the idle running clock FCLK directly to Cortex.

④, sent to APB1 divider. APB1 divider can select 1, 2, 4, 8, 16 frequency division, one of its outputs is used for APB1 peripherals (PCLK1, maximum frequency 36MHz), and the other is used for APB1 peripherals (PCLK1, maximum frequency 36MHz).

The clock output is sent to the timer 2, 3, 4 frequency multiplier. The frequency multiplier can select 1 or 2 times, and the clock output is used by timer 2, 3, 4.

⑤, sent to APB2 divider. APB2 divider can select 1, 2, 4, 8, 16 frequency division, one of its outputs is used for APB2 peripherals (PCLK2, maximum frequency 72MHz), and the other is used for APB2 peripherals (PCLK2, maximum frequency 72MHz).

The APB2 divider has one output for the Timer 1 frequency multiplier. The frequency multiplier can select 1 or 2 times the frequency, and the clock output is used by Timer 1.

The ADC frequency divider is used and the divided frequency is sent to the ADC module for use. The ADC frequency divider can be selected as 2, 4, 6, or 8 divisions.

Among the above clock outputs, many have enable control, such as AHB bus clock, core clock, various APB1 peripherals, APB2 peripherals, etc.

When you use the module, remember to enable the corresponding clock first.

It should be noted that the timer multiplier, when the APB frequency division is 1, its multiplier value is 1, otherwise its multiplier value is 2.

The devices connected to APB1 (low-speed peripherals) are: power interface, backup interface, CAN, USB, I2C1, I2C2, UART2, UART3, SPI2, window watchdog, Timer2,

Timer3, Timer4. Note that although the USB module requires a separate 48MHz clock signal, it should not be the clock for the USB module to work, but only for the serial interface.

The clock used by the engine (SIE). The clock for the USB module to work should be provided by APB1.

The devices connected to APB2 (high-speed peripherals) are: UART1, SPI1, Timer1, ADC1, ADC2, all common IO ports (PA~PE), and second function IO ports. [page]

For a single-chip microcomputer system, the clock settings of the CPU, bus, and peripherals are very important, because without a clock there is no timing.

Since the clock is an inside-out thing, the specific setting starts from the register.

The RCC register structure, RCC_TypeDeff, is defined in the file "stm32f10x.h" as follows: (v3.4 library)

Line 1059->Line 1081.

1. typedef struct

2. {

3. __IO uint32_t CR;

4. __IO uint32_t CFGR;

5. __IO uint32_t CIR;

6. __IO uint32_t APB2RSTR;

7. __IO uint32_t APB1RSTR;

8. __IO uint32_t AHBENR;

9. __IO uint32_t APB2ENR;

10. __IO uint32_t APB1ENR;

11. __IO uint32_t BDCR;

12. __IO uint32_t CSR;

13.

14. #ifdef STM32F10X_CL

15. __IO uint32_t AHBRSTR;

16. __IO uint32_t CFGR2;

17. #endif

18.

19. #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)

20. uint32_t RESERVED0;

21. __IO uint32_t CFGR2;

22. #endif

23. }RCC_TypeDef;

Generally, there is only an 8Mhz crystal oscillator on the board, but the maximum operating frequency of the enhanced version is 72Mhz, so it is obviously necessary to use PLL to multiply the frequency by 9 times. These settings need to be completed during the initialization phase.

Using HSE clock, the program sets the clock parameters process:

1. Reset the RCC register to the default value RCC_DeInit;

2. Turn on the external high-speed clock crystal HSE RCC_HSEConfig (RCC_HSE_ON);

3. Wait for the external high-speed clock crystal to work HSEStartUpStatus = RCC_WaitForHSEStartUp();

4. Set AHB clock RCC_HCLKConfig;

5. Set high-speed AHB clock RCC_PCLK2Config;

6. Set the low speed AHB clock RCC_PCLK1Config;

7. Set PLL RCC_PLLConfig;

8. Enable PLL RCC_PLLCmd(ENABLE);

9. Wait for PLL to work while (RCC_GetFlagStatus (RCC_FLAG_PLLRDY) == RESET)

10. Set the system clock RCC_SYSCLKConfig;

11. Determine whether PLL is the system clock while (RCC_GetSYSCLKSource() != 0x08)

12. Open the peripheral clock RCC_APB2PeriphClockCmd()/RCC_APB1PeriphClockCmd() to be used

For the convenience of explanation, we will use the RCC setting function of the following routine and explain it in the form of Chinese comments:

1. static void RCC_Config(void)

2. {

5. RCC_DeInit();

8. RCC_HSEConfig(RCC_HSE_ON);

10.

11. HSEStartUpStatus = RCC_WaitForHSEStartUp();

12.

13. if (HSEStartUpStatus == SUCCESS)

14.

15.

16. FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);

17.

18.

19. FLASH_SetLatency(FLASH_Latency_2);

20.

twenty one.

22. RCC_HCLKConfig(RCC_SYSCLK_Div1);

twenty three.

twenty four.

25. RCC_PCLK2Config(RCC_HCLK_Div1);

26.

27.

28. RCC_PCLK1Config(RCC_HCLK_Div2);

29.

30.

31. RCC_ADCCLKConfig(RCC_PCLK2_Div6);

32.

33.

34. //This sentence is very important

35.

36. RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);

37.

38.

39. RCC_PLLCmd(ENABLE);

40.

41.

42.

43. while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)

44. {}

45.

46.

47. RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);

48.

49.

50. while (RCC_GetSYSCLKSource() != 0x08)

51. {}

52. }

53.

54.

55. // Enable the peripheral interface bus clock. Pay attention to the affiliation of each peripheral. Different chips have different allocations. You can check the manual when the time comes.

Can

56. RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);

57.

58. RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |

59. RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG |

60. RCC_APB2Periph_AFIO, ENABLE);

61. }

From the above program, we can see that the system clock setting is relatively complicated. The more peripherals there are, the more factors need to be considered. At the same time, this setting also has rules to follow.

There are also sequential specifications, which should be noted in the application. For example, the PLL settings need to be made before enabling, and the parameters cannot be changed once the PLL is enabled.

After this setting, since my circuit board has an 8Mhz crystal oscillator, the system clock is 72Mhz, the high-speed bus and low-speed bus 2 are both 72Mhz, and the low-speed bus 1 is 36Mhz.

The ADC clock is 12Mhz, and the USB clock can be divided by 1.5 to achieve 48Mhz data transmission.

For general clock settings, you need to first consider the source of the system clock, whether it is an internal RC, an external crystal, or an external oscillator, and whether a PLL is required. Then consider the internal bus and external

The bus, and finally the peripheral clock signal. The principle of multiplying the frequency first as the CPU clock, and then dividing the frequency from the inside out, and the lower level accommodating the upper level is somewhat similar to the specification of PCB drawing.

The same applies here.

Note:

In STM32, the devices connected to APB1 (low-speed peripherals) are: power interface, backup interface, CAN, USB, I2C1, I2C2, UART2, UART3, SPI2, window watchdog, Timer2,

Timer3, Timer4.

The devices connected to APB2 (high-speed peripherals) are: GPIO_A-E, USART1, ADC1, ADC2, ADC3, TIM1, TIM8, SPI1, ALL.

Program example:

APB1 (low-speed peripherals)

RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN, ENABLE);

APB2 (High-speed peripherals)

RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);

RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);

Keywords：STM32 Reference address：Detailed explanation of STM32 clock

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