MSP430 Learning Notes (4) ADC12

1. A few terms:

a) Resolution (LSB): It indicates the change in input analog voltage required for the output digital quantity to change by one adjacent digital number. It is defined as the full-scale voltage of the converter and 2 to the power of n, where n is the number of bits of the ADC.

b) Quantization error: The error caused by the discrete value (quantization) of the analog value by a finite number. Therefore, the quantization error is theoretically one unit resolution, i.e., plus or minus 12LSB.

c) Conversion accuracy: reflects the difference between the actual ADC module and the ideal ADC module in terms of quantization when performing analog-to-digital conversion.

d) Conversion time: refers to the time required for the ADC to complete an analog/digital conversion.

2. Structure:            

3. Reference voltage generator:

a) Refers to the required reference signal, usually a voltage reference. The MSP430 ADC12 has a built-in reference power supply with 6 programmable options.

b) Analog multiplexer: When multiple analog signals are sampled and A/D converted, in order to share a conversion core, the analog multiplexer needs to connect the multiple analog signals in a time-sharing manner, sampling and converting one signal at a time.

c) MSP430 ADC12 is configured with 8 external channels and 4 internal channels. It can realize external 8-channel analog signal input through A0~A7. The 4 internal channels can use multiple reference voltages and the output of the internal temperature sensor as analog input signals to be converted.

d) 12-bit converter core with sample and hold function: The ADC12 core is a 12-bit analog-to-digital converter that can store the result in the converter memory. The core uses two programmable reference voltages (Vr+ and Vr-) to define the maximum and minimum values ​​of the conversion. The formula is: Nadc = 4095 * (Vin - Vr) / (Vr+ -Vr)

e) Timing control circuit required for sampling and conversion: Provides various signals required for sampling and conversion: ADC12CLK conversion clock, SAMPCON sampling and conversion signal, SHT controlled sampling period, SHS controlled sampling trigger source selection, ADC12SSEL selected core clock source and AC12DIV selected division coefficient.

4. ADC12 register:

a) Conversion control register ADC12CTL0

                        i. ADC12SC sampling/conversion control bit: When ENC = 1, ISSH = 0 and SHP = 1, ADC12SC starts A/D conversion from 0 to 1. ADC12SC automatically resets after the A/D conversion is completed. When SHP = 0, ADC12SC maintains high-level sampling, and a conversion is started when ADC12SC is reset.

                      ii. ENC conversion enable bit: 0 is the initial state, A/D conversion cannot be started; 1 is the first conversion started by the rising edge of SAMPCON.

                     iii. ADC12TIVE conversion time overflow interrupt enable bit: 0: no conversion time overflow occurs, 1: conversion time overflow occurs.

                     iv. ADC12OVIE overflow interrupt enable bit: 0 means no overflow occurs, 1 means overflow occurs.

                      v. ADC12ON: ADC12 core control bit: 0 means turning off the ADC12 core, 1 means turning it on.

                     vi. REFON: Reference voltage control bit, 0 means the internal reference voltage generator is turned off, 1 means the internal reference voltage generator is turned on.

                   vii. 2.5V internal reference voltage voltage value selection bit: 0 for 1.5V, 1 for 2.5V.

                  viii. MSC multiple sampling/conversion bit: It is only valid when SHP = 1. 0 means that each conversion requires the rising edge of the SHI signal to trigger the sampling timer. 1 means that only the first conversion is triggered by the rising edge of the SHI signal. The subsequent sampling conversion will be performed immediately after the previous conversion is completed.

                     ix. SHT1/SHT0 sample-and-hold timer: defines the relationship between the conversion sampling timing and the sampling clock ADC12CLK stored in the conversion result registers ADC12MEM8_ADC12MEM15 and ADC12MEM0~ADC12MEM7. The sampling period is n times the ADC12CLK period multiplied by 4. N is 2 to the power of SHITx. [page]

b) Conversion control register ADC12CTL1

                        i. CSStartAdd conversion storage address bit, can define a single conversion address or the first address of a sequence conversion.

                      ii. SHS sampling input trigger source selection: 0 is ADC12SC, 1 is Timer_A.OUT1, 2 is Timer_B.OUT0, 3 is Timer_B.OUT1.

                     iii. SHP sampling signal (SAMPCON) selection control bit: 0 means the signal source comes from the sampling trigger input signal, 1 means the signal source comes from the sampling timer, and the sampling timer is triggered by the rising edge of the sampling input signal.

                     iv. ISSH sampling input signal direction control bit: 0 means the sampling input signal is input in the same direction, 1 means it is input in the opposite direction.

                      v. ADC12DIV: ADC12 clock source division factor is selected.

                     vi. ADC12SSEL ADC12 core clock source selection: 0 is ADC12 internal clock source ADC12OSC (default), 1 is ACLK, 2 is MCLK, and 3 is SMCLK.

                   vii. CONSEQ conversion mode selection bit: 0 is single-channel single conversion mode, 1 is sequential channel single conversion mode, 2 is sequential channel multiple conversion mode, and 3 is sequential channel multiple conversion mode.

                  viii. ADC12BUSY ADC12 busy flag: 0 means no activity, 1 means busy.

c) ADC12MEM0~ADC12MEM15 conversion storage register: 16-bit register used to store A/D conversion results, only the lower 12 bits are used.

d) ADC12MCTLx conversion memory control register:

                        i. EOS: Sequence end control bit: 0 means the sequence has not ended, 1 means it has ended.

                      ii. Sref reference voltage source selection bit:                                             

                     iii. INCH selects the analog input channel: The 4-bit binary number represents the selected analog input channel:

e) ADC12IFG interrupt flag register: ADC12IFGx is set to indicate that the conversion is completed and the conversion result has been loaded into the conversion storage register; ADC12IFGx is reset to indicate that ADC12MEMx is accessed.

f) ADC12IE interrupt enable register: 1 allows the interrupt request service that occurs when the corresponding ADC12IFGx is set, and 0 prohibits the interrupt request service that occurs when ADC12IFGx is set.

g) ADC12IV interrupt vector register.

5. Initialization code