LPC2103 timer0 and timer1

 Timer/Counter Timer0 and Timer1
         Page187
 
 
         The timer/counter is programmed to count cycles under the peripheral clock (PCLK) or the externally provided clock. It can selectively generate an interrupt or perform other operations after the specified timing value is reached based on four match registers. It also includes four capture inputs to capture the timing value of the changing signal and optionally generate an interrupt.
 
 
Pin description
 

Pins	type	describe
CAP0.2.0 CAP1.3.0	Input	Capture Signals - Capture pin changes can be configured to increment the timer count in the capture register and to generate an interrupt as desired. The following is a list of capture signals: CAP0.0: P0.2 CAP0.1: P0.4 CAP0.2: P0.6 CAP1.0: P0.10 CAP1.1: P0.11 CAP1.2: P0.17 CAP1.3: P0.18
MAT0.2.0 MAT1.3.0	Output	External Match Output 0/1 - When a match register 0/1 equals the timer count value, this output may toggle, go high, go low, or remain unchanged. The External Match Register (EMR) and the PWM Control Register (PWMCON) control the function of this output. The following is a list of the capture signals: ? MAT0.0: P0.3 ? MAT0.1: P0.5 ? MAT0.2: P0.16 ? MAT1.0: P0.12 ? MAT1.1: P0.13 ? MAT1.2: P0.19 ? MAT1.3: P0.20

 
 
 
Register description
 
Below only lists the various registers of Timer 1 for explanation, and the other Timers 0/2/3 are similar.
 
/************************************** Timer 1 *************************************/
/************************* Special register of Timer 1 *********************************/
 
//Interrupt register
#define T1IR (*((volatile unsigned char *) 0xE0008000))             
Reading the value of this register can determine which of the 8 interrupt sources has caused an interrupt. Writing 1 clears the interrupt, and writing 0 has no effect. This register includes four match interrupts and four capture interrupts. Once an interrupt occurs, the corresponding position is high, otherwise it is low.

Bit	Signal	describe	Reset value
0	MR0 interrupt	Match channel 0 interrupt flag	0
1	MR1 interrupt	Match channel 1 interrupt flag	0
2	MR2 interrupt	Match channel 2 interrupt flag	0
3	MR3 interrupt	Match channel 3 interrupt flag	0
4	CR0 interrupt	Capture channel 0 event interrupt flag	0
5	CR1 interrupt	Capture channel 1 event interrupt flag	0
6	CR2 interrupt	Capture channel 2 event interrupt flag	0
7	CR3 interrupt	Capture channel 3 event interrupt flag	0

 
//Timer control register
#define T1TCR (*((volatile unsigned char *) 0xE0008004))            
       This register is used to control the operation of the timer/counter.

Bit	Signal	describe	Reset value
0	Counter Enable	When it is 1, the timer counter and frequency divider counter are enabled. When it is 0, the counter is disabled.	0
1	Counter Reset	When it is 1, the timer counter and frequency divider counter are reset synchronously on the next rising edge of PCLK. The counter reset is maintained until this bit returns to 0.	0
7:2		reserve	NA

 
 
//Timer counter
#define T1TC (*((volatile unsigned long *) 0xE0008008))            
       When the frequency division counter (PC) reaches the predetermined value, the 32-bit timer counter increases by 1. It is reset after reaching the limit value. When the TC count reaches the maximum value 0xffffffff, it increases by 1 and resets to 0x00000000. This event will not cause an interrupt, but the match register can be used to detect overflow if necessary.
 
//Frequency division register
#define T1PR (*((volatile unsigned long *) 0xE000800C))             
       The 32-bit frequency division register specifies the maximum count value of the frequency division counter (PC).
 
//Frequency division counter register
#define T1PC (*((volatile unsigned long *) 0xE0008010))            
       The 32-bit frequency division counter divides PCLK by some constant value before using it for the timing timer. The frequency divider counter increases by 1 for each PCLK clock. When it reaches the value stored in the frequency divider register (PR), the timer counter increases by 1 and the frequency divider counter is reset at the next PCLK. In other words, if PC=1, then PC is reset every 2 PCLKs. [page]
 
//Match control register
#define T1MCR (*((volatile unsigned short *) 0xE0008014))            
       The match control register is used to control what operation will be performed when a match register matches the timer counter.

Bit	Signal	describe	Reset value
0	MR0I	When writing 1, an interrupt will be generated when MR0 matches TC; writing 0 turns off this function.	0
1	MR0R	When writing 1, MR0 will be reset when it matches TC; writing 0 turns off this function.	0
2	MR0S	When writing 1, when MR0 matches TC, the PC and TC counting will stop and TCR[0] will be pulled low (0); writing 0 disables this function.	0
3	MR1I	When writing 1, an interrupt will be generated when MR1 matches TC; writing 0 turns off this function.	0
4	MR1R	When writing 1, MR1 will be reset when it matches TC; writing 0 turns off this function.	0
5	MR1S	When writing 1, when MR1 matches TC, the PC and TC counts will stop and TCR[0] will be pulled low (0); writing 0 disables this function.	0
6	MR2I	When writing 1, an interrupt will be generated when MR2 matches TC; writing 0 turns off this function.	0
7	MR2R	When writing 1, MR2 will be reset when it matches TC; writing 0 turns off this function.	0
8	MR2S	When writing 1, when MR2 matches TC, the PC and TC counting will stop and TCR[0] will be pulled low (0); writing 0 disables this function.	0
9	MR3I	When writing 1, an interrupt will be generated when MR3 matches TC; writing 0 turns off this function.	0
10	MR3R	When writing 1, MR3 will be reset when it matches TC; writing 0 turns off this function.	0
11	MR3S	When writing 1, when MR3 matches TC, the PC and TC counting will stop and TCR[0] will be pulled low (0); writing 0 disables this function.	0
15:12		reserve

 
//Match Registers
//Match Register 0
#define T1MR0 (*((volatile unsigned long *) 0xE0008018))             
//Match Register 1
#define T1MR1 (*((volatile unsigned long *) 0xE000801C))             
//Match Register 2
#define T1MR2 (*((volatile unsigned long *) 0xE0008020))             
//Match Register 3
#define T1MR3 (*((volatile unsigned long *) 0xE0008024))            
       The value of the match register will be continuously compared with the value of the timer counter (TC). When the two are equal, the corresponding action will be automatically triggered. This action may generate an interrupt, reset the timer counter, or stop the timer. The behavior is determined by the setting of the MCR register.
 
//Capture control register
#define T1CCR (*((volatile unsigned short *) 0xE0008028))            
       The capture control register is used to control whether one of the four capture registers is loaded with the timer counter value when a capture event occurs, and whether the capture event generates an interrupt.

Bit	Signal	describe	Reset value
0	CAP0RE	When writing 1, the rising edge of CAPn.0 is captured, and when the rising edge comes, it will cause CR0 to load the TC value.	0
1	CAP0FE	When writing 1, the falling edge of CAPn.0 is captured, and when the falling edge comes, it will cause CR0 to load the TC value.	0
2	CAP0I	When writing 1, CAPn.0 event interrupt, CAPn.0 event will generate an interrupt.	0
3	CAP1RE	When writing 1, the rising edge of CAPn.1 is captured, and when the rising edge comes, it will cause CR1 to load the TC value.	0
4	CAP1FE	When writing 1, the falling edge of CAPn.1 is captured, and when the falling edge comes, it will cause CR1 to load the TC value.	0
5	CAP1I	When writing 1, CAPn.1 event interrupt, CAPn.1 event will generate an interrupt.	0
6	CAP2RE	When writing 1, the rising edge of CAPn.2 is captured, and when the rising edge arrives, it will cause CR2 to load the TC value.	0
7	CAP2FE	When writing 1, the falling edge of CAPn.2 is captured, and when the falling edge comes, it will cause CR2 to load the TC value.	0
8	CAP2I	When writing 1, CAPn.2 event interrupt, CAPn.2 event will generate an interrupt.	0
9	CAP3RE	When writing 1, the rising edge of CAPn.3 is captured, and when the rising edge comes, it will cause CR3 to load the TC value.	0
10	CAP3FE	When writing 1, the falling edge of CAPn.3 is captured, and when the falling edge comes, it will cause CR3 to load the TC value.	0
11	CAP3I	When writing 1, CAPn.3 event interrupt, CAPn.3 event will generate an interrupt.	0
15:12		reserve	NA

 
 
//Capture Registers
//Capture Register 0
#define T1CR0 (*((volatile unsigned long *) 0xE000802C))             
//Capture Register 1
#define T1CR1 (*((volatile unsigned long *) 0xE0008030))            
 //Capture Register 2
#define T1CR2 (*((volatile unsigned long *) 0xE0008034))             
//Capture Register 3
#define T1CR3 (*((volatile unsigned long *) 0xE0008038))             
       Each capture register is associated with a device pin. The capture register may be loaded with the timer counter value when a specified event occurs on the external pin. The settings of the capture control register determine whether the capture function is enabled and whether the trigger event is the rising edge, falling edge, or both edges (including the rising and falling edges) of the associated pin.
 
//External match register
#define T1EMR (*((volatile unsigned short *) 0xE000803C))           
       The external match register controls the external match pin MAT(0-3) and can read its status.

Bit	Signal	describe	Reset value
0	EM0	External Match 0. This bit reflects the status of the output MAT0.0/MAT1.0. When TC matches MR0, the timer output can be high, low, or unchanged. EMR[5:4] controls the output function.	0
1	EM1	External Match 1. This bit reflects the status of the output MAT0.1/MAT1.1. When TC matches MR1, the timer output can be high, low, or unchanged. EMR[7:6] controls the output function.	0
2	EM2	External Match 2. This bit reflects the status of output MAT0.2/MAT1.2. When TC matches MR2, the timer output can be high, low, or unchanged. EMR[9:8] controls the output function.	0
3	EM3	External Match 3. This bit reflects the status of the output MAT0.3/MAT1.3. When TC and MR3 match, the timer output can be high, low, or unchanged. EMR[11:10] controls the output function.	0
5:4	EMC0	External Match Control 0	00
7:6	EMC1	External Match Control 1	00
9:8	EMC2	External Match Control 2	00
11:10	EMC3	External Match Control 3	00
15:12		reserve	NA

External Match Control
00 - Do nothing
01 - Clear the corresponding external match bit/output 0
10 - Set the corresponding external match bit/output 1
11 - Toggle the corresponding External Match bit/output
 
//Count Control Register
#define T1CTCR (*((volatile unsigned long *) 0xE0008070))            
       This register is used to select the timer or counter mode. In the counting mode, it is also used to select the pin and edge for counting.
       In the counter mode, the CAP input (selected by bit3:2 of the CTCR register) is sampled at the rising edge of each PCLK clock. After comparing two consecutive sampled values ​​of CAP, one of the following four events is generated: the rising edge, falling edge, edge change, and no change of the selected CAP input. Only when the event selected by bit1:0 of ​​the CTCR register is recognized, the timer counter register will increase by 1.
       In fact, the externally provided clock running counter has its limitations. Two consecutive rising edges of PCLK can only be used to identify a change edge of the CAP selection input, and the CAP input frequency cannot exceed half of the PCLK clock. Therefore, the high or low level of the same CAP input must be maintained for at least 1/PCLK time.

Bit	Signal	describe	Reset value
1:0	Counter/Timer mode	00——Timer mode, PC value increases by 1 after each rising edge of PCLK, or TC increases by 1 when PC is reset; 01——Counter mode, TC value increases by 1 after the rising edge of CAP selected by bit3:2; 10——Counter mode, TC value increases by 1 after the falling edge of CAP selected by bit3:2; 11——Counter mode, TC value increases by 1 after the edge of CAP selected by bit3:2 changes;	00
3:2	Count input select	00——CAP1.0 for Timer1 01——CAP1.1 for Timer1 10——CAP1.2 for Timer1 11——CAP1.3 for Timer1	00
7:4		reserve	NA

 
//PWM control register
#define PWM1CON (*((volatile unsigned long *) 0xE0008074))             

Bit	Signal	describe	Reset value
0	PWM enable	1——PWM mode of MATn.0 is enabled 0——MATn.0 is controlled by EM0	0
1	PWM enable	1——PWM mode of MATn.1 is enabled 0——MATn.1 is controlled by EM0	0
2	PWM enable	1——PWM mode of MATn.2 is enabled 0——MATn.2 is controlled by EM0	0
3	PWM enable	1——PWM mode of MATn.3 is enabled 0——MATn.3 is controlled by EM0	0
32:4		reserve	NA