S3C44B0X Application Design - Memory Interface Design

Introduction 

Samsung's S3C44B0X 16/32-bit RISC processor is designed to provide a low-cost, high-performance solution for handheld devices. S3C44B0X provides the following configurations: 

2.5V ARM7TDMI core with 8KB cache (SAMBA bus structure up to 75MHZ); optional internal SRAM; 

external storage controller (FP/EDO/SDRAM control, chip select logic); 

LCD Controller (supports up to 256 colors STN), LCD controller with dedicated DMA (supports up to 256 colors DSTN);

two general DMA channels, two peripheral DMA channels with external request pins; 

two UARTs/one SIO (IRDA1.0, 16-byte FIFO); 

one multi-master IIC bus controller and one IIS bus controller l 5 PWM timers and one internal timer; 

watchdog timer; 

71-bit general I/O interface/8 external interrupt sources; 

power control: Normal, Slow, Idle and Stop modes; 

8-channel 10-bit ADC; 

real-time clock (RTC) with Hitachi function; 

on-chip PLL Clock generator Therefore, you can use S3C44B0X to make different systems 

Application system of S3C44B0 

If your product needs to access the Internet, Samsung's 16/32-bit RISC S3C44B0X microcontroller can reduce your cost. The following are some systems that can be designed with S3C44B0X.  

l GPS phone l PDA (Personal Digital Assistant) 

l Fish Finder l Handheld game console l Fingerprint recognition system l TWM (Two Way Messaging) l Terminal car navigation system l MP3 player and so on. 

Memory interface design 

Boot ROM design When the system is reset, S3C44B0X accesses address 0x00000000. After reset, S3C44B0X must configure some system variables. Therefore, this special code (BOOT ROM image) should be located at address 0x00000000. The boot ROM can have different widths of data bus. The bus width is controlled by the OM[1:0] pin. 







Compile and burn a byte ROM image

When compiling a byte ROM image, you should use the binary file from the compilation and linking to design a half-word Boot ROM with byte EEPROM/FLASH. Figure 4-2 shows a half-word Boot ROM designed with byte EEPROM/FLASH. [page]



Figure 4-2 shows a half-word Boot ROM designed with byte EEPROM/FLASH. Compile and burn a half-word ROM image designed with byte EEPROM/Flash. When making a half-word ROM image, it can be divided into two files EVEN and ODD. Figure 4-3 shows a half-word Boot ROM designed with half-word EEPROM/FLASH. 




Figure 4-3 shows a half-word Boot ROM designed with half-word EEPROM/FLASH. Word Boot ROM designed with word EEPROM/FLASH. 



Figure 4-4 shows a word boot ROM designed with byte EEPROM/Flash. Compile and burn a word ROM image designed with byte EEPROM/Flash. When you make a word ROM image, you can divide it into four image files.