Design and implementation of network interface module based on AX88796B

Today, with the increasing popularity of network technology, the instruments, data acquisition and control equipment in industrial sites are becoming more and more networked, and the combination of industrial automation and networks is becoming closer and closer. It has become a trend to combine Ethernet and embedded systems for industrial control.

AX88796B is a low-pin Ethernet control chip designed for embedded and industrial Ethernet applications launched by Asix. It integrates 10/100Mb/s adaptive media access layer MAC and physical layer transceiver PHY and 8K×16-bit SRAM. AX88796B can be used in the commercial grade 0~70C and industrial grade -40C~85C temperature range. AX88796B supports MCS-51 series, 80186 series, ISA bus and SRAM-like interface types. It performs 10Mb/s and 100Mb/s Ethernet control functions based on IEEE802.3/IEEE802.3u LAN standards, and provides a send queue function to enhance the sending performance of the standard NE2000.

The AT91R40008 microcontroller is an embedded microcontroller with a 32-bit RISC structure based on the ARM7TDMI core, which is very suitable for industrial real-time control applications. The LQFP package of the AX88796B pin reduces the PCB space and is compatible with NE2000. It is easy to program and its driver can be easily and quickly ported to many embedded systems. Therefore, combining the advantages of the above two chips, we choose AX88796B and AT91R40008 as the solution for embedded network applications in industrial real-time control, which has good industrial application value and prospects.

                                        Figure 1 AX88796B internal structure diagram

I. AX88796B internal structure and working principle

1 AX88796B internal structure

When the network card is powered on and reset, the EEPROM interface can access data through the SMI/EEPROM register with an offset of 14H in the CSR. The MAC address is read from the EEPROM and automatically loaded into the internal storage area with addresses 0000h~001fh and 0400h~040fh. If EEPROM is not used, a MAC address is manually assigned to it every time the network card is initialized at power-on.

The AX88796B has a 16KB (0x4000~0x7fff) SRAM inside. The SRAM is a dual-port SRAM that can be read and written by the network card and the user at the same time. Part of this address space is reserved for storing a buffer ring structure, and the other part can be used by the user. In this design, all 16KB of SRAM is used to receive and send data packets. The local DMA receives messages through this buffer ring structure. This structure consists of a series of adjacent fixed-length 256B buffers, each 256 bytes is called a page, and there are 64 pages in total. The page address is the high 8 bits of the address, and the page address is 0x00~0xff. Among them, 0x40~0x4B is the send buffer of the network card, a total of 12 pages, which can just store 2 largest Ethernet packets, so we divide the send buffer into two parts and send them in turn. Use 0x4c~0x7f, a total of 52 pages, as the receive buffer of the network card. The SRAM space structure and the send and receive buffer structure of AX88796B are shown in Figures 2 and 3.

                                       Figure 2 SRAM spatial structure

                                      Figure 3 Transceiver Buffer

2 Working Principle of AX88796B

Four registers are used to control the operation of the receive buffer. Page Start Address Register (PSTART) and Page Stop Address Register (PSTOP) define the start and end page numbers of the receive buffer, forming a receive buffer ring. The Current Page Address Register points to the first buffer for storing data packets. The Boundary Pointer Register points to the first data packet in the buffer ring that has not been read by the host. If the local DMA address is equal to the value of the Boundary Pointer Register, the receiving process is terminated. The Boundary Pointer is also used to initialize the remote DMA to move a data packet. When the data packet is moved, the Boundary Pointer also increases forward. In this way, the Current Page Register acts as a write pointer and the Boundary Pointer acts as a read pointer. When a data packet is received, it is stored starting from the page number specified in the PSR. If a 256B buffer is not enough, the DMA will perform a forward connection to connect the next buffer to store the rest of the data packet. When connecting, the buffers must be continuous, and a data packet will always be stored in adjacent buffers. Before connecting to the next buffer, the buffer management logic will perform two comparisons. First, it compares whether the DMA address of the next buffer is equal to the page stop register. If they are equal, the DMA address is restored to the address stored in the page start address register. Secondly, it compares with the boundary pointer register. If they are equal, the message receiving process is terminated. The boundary pointer register can prevent the data in the buffer from being overwritten before it is read out. [page]

To send and receive data packets, the SRAM inside the AX88796B must be read and written through DMA. DMA is divided into remote DMA and local DMA. The CPU reading and writing data from the SRAM of the network card is called remote DMA. The AX88796B reading and writing SRAM is called local DMA. The process of receiving data packets: When the data packet reaches the MAC layer of the network card, the local DMA first transmits the message arriving at the MAC layer to the memory of the network card, and the host CPU then reads the data packet from the memory of the network card through the remote DMA channel. Data packet transmission process: The host CPU sends the data packet to be sent to the memory of the network card through the remote DMA. The local DMA transmits the data packet to the MAC layer, and then sends it to the network through the internal PHY layer.

2. Network interface hardware design

1. AX88796B pin configuration

The connection modes of AX88796B and CPU include MCS51 mode, ISA mode, and 186 mode. This scheme uses ISA 8-bit mode. The chip select pin CSn, read and write signals RDn, WRn, and RSTn are all low-level valid, and can be connected to the corresponding pins of AT91r40008 respectively. The data lines SD0~SD15 of AX88796B are connected to DATA[0:15] of AT91r40008, and can be configured as 16-bit or 8-bit DMA data transmission mode through software. The IRQ of AX88796B is programmable. The interrupt request signal can be configured by BTCR or EEPROM to select its trigger mode and interrupt I/O buffer type. The AT91r40008 interrupt trigger mode should be consistent with the configuration of BTCR. Other important pins such as IOIS16, PME, EECE, and EECK are left floating in this design. The pin configuration should be determined according to the manual instructions and design plan of the network card chip.

For the operation of the AX88796B control status register (CSR), its base address needs to be determined. The selection of the base address should be determined according to the address and chip select signal of the programmable external bus EBI of AT91r40008.

The EBI of AT91r40008 handles the access operation located in the address space 0x00400000~0xFFC00000. During the access process, it will generate a control access signal for the external device. After the network card register address space is mapped into EBI, the register read and write of the network card can be controlled by directly operating the EBI address space. For each peripheral device mapped into the EBI interface, the number of waiting cycles, data floating time, data bus width (8 bits or 16 bits), etc. can be programmed.

2 AT91r40008 and AX88796B interface circuit

                                   Figure 4 Hardware connection schematic diagram

III. Driver design of AX88796B

The network card driver of AX88796B is the interface between the processor CPU and the network card hardware. The network card driver mainly includes the following parts: network card initialization; data packet reception and transmission; interrupt processing subroutine.

1 Network card initialization

In the process of network card initialization, in addition to completing the definition and assignment of relevant registers, the construction of the receiving buffer ring must also be completed. All registers of AX88796B except the data port register are 8-bit data width. The data port register can be set to 8 or 16 bits wide by configuring WTS in the DCR register.

AX88796B divides the registers with offsets of 01h to 0fh into 4 pages (Page0 to Page3) for operation. There are only 3 pages of registers compatible with NE2000 (Page0 to Page2). Initialization requires setting the relevant registers of page 0 and page 1. The registers of page 2 are read-only and cannot be set. The registers of page 3 are not compatible with NE2000 and do not need to be set. The initialization function mainly completes the following tasks.

/*AX88796B_init*/

/*Call the reset subroutine to reset the AX88796B. There are two reset methods: one is hardware reset, which resets the AX88796B by pulling up or down the RESET pin; the other is software reset, which resets the AX88796B by reading data from port 0x1f. */

ReadByte(RESET);

WriteByte(RESET,0xff);

delay(3000);

WriteByte(IMR,0);/*Initialize the interrupt mask register IMR, write 0x00, and disable all interrupt requests. */

WriteByte(CR,0x61);/*Select page 1 and stop AX88796B. */

delay(1000);

WriteByte(CPR,0x4C);/*Initialize the receive buffer ring write page pointer CPR＝PSTART*/

WriteByte(PAR0～PAR5,MAC);/*Set the MAC address of the network card chip and clear the multicast address register. */

WriteByte(MAR0～MAR7,0);

WriteByte(CR,0x21);/*Stop the network card and switch to page 0. */

delay(1000);

WriteByte(BNRY,0x79);/*Write the boundary pointer register (BNRY) to 0x79; */

WriteByte(PSTART,0x4c);/*Set the start page address of the receive buffer to 0x4c; */

WriteByte(PSTOP,0x80);/*The end page address of the PSTOP receive buffer is 0x80; */

WriteByte(TPSR,0x40);/*The start address of the TPSR send page is 0x40; */

WriteByte(DCR,0x80);/*Set the data configuration register to 8-bit data transmission mode. */ /

*Set the receive configuration register to 0x4C, so that the receive buffer only receives broadcast address data packets and multicast address packets. */

WriteByte(RCR,0x4C);

/*Set TCR transmission configuration register to 0x80, use full-duplex mode, automatically fill when the data packet length is less than 60 bytes, and add CRC check when sending. */

WriteByte(TCR,0x80);

WriteByte(ISR,0xFF);/*Clear interrupt status register. */

WriteByte(IMR,0x11);/*Allow overwrite interrupt and data packet reception interrupt. */

WriteByte(BTCR,0x30);/*Interrupt trigger mode is high level effective, IRQ output is push-pull drive mode*/

WriteByte(CR,0x22);/*Start chip, AX88796B initialization is completed. */

delay(1000);

wrcurpge=read(CPR);

rdnxtpge=wrcurpge;[page]

2 Data packet transmission and reception

There are two ways to determine whether AX88796B has received a new data packet: round-robin and interrupt. The single-chip microcomputer uses the round-robin method more often. In order to improve CPU performance and real-time requirements, the interrupt method is used here. When the network card receives a new data packet, it enters an interrupt. First, it determines whether CPR is equal to BNRY. If they are equal, it means that the receiving buffer is full, and then the receiving data packet is stopped without overwriting the old data; if they are not equal, the starting address of the data packet to be read in the receiving buffer is written into the RSAR[0,1] register, and the first 4 bytes of the data packet are written into the RBCR[0,1] register, and the remote DMA read command is started. By reading 4 information bytes, the length of the data packet to be read, the receiving status and the pointer information of the next page to be read are obtained. Then, through the remote DMA read command, the data packet is read from the network card SRAM into the CPU memory, and the read page pointer register BNRY is updated. Every time the CPU reads a page of data from the network card memory, BNRY is increased by one. This needs to be implemented through a program. The network card writes the received data packets into the receive buffer through CPR. After each page is written, CPR will automatically increase by one. When it reaches the last empty page (here PSTOP=0x80), CPR will automatically restore to the first page of the receive buffer (PSTART=0x4c). The key codes for network card receiving are as follows:

/*AX88796B_receive*/

uint8 rcvinfo,i;

uint16 pktlength,index; 

/*Get the information of the data packet to be read and save it in the rcvinfo array*/

WriteByte(RSAR0,0x00);

WriteByte(idx,RSAR1,rdnxtpge);

WriteByte(RBCR0,0x04);

WriteByte(RBCR1,0x00);

WriteByte(CR,0x0A);

for(i=0;i<4;i++)

rcvinfo=*((uint8*)(DP_PORT+Base_addr));

pktlength=rcvinfo+(rcvinfo*256)-4;

/*According to the length pktlength of the data packet to be read, read the data packet into the CPU memory Buf*/

WriteByte(RSAR0,0x4);

WriteByte(RSAR1,rdnxtpge);

WriteByte(RBCR0,(uint8)(pktlength&0x00ff));

WriteByte(RBCR1,(uint8)(pktlength>>8));

WriteByte(CR,0x0A);

ReadData(uint16*Buf,uint16 length);

/*Update BNRY pointer and return pktlength value*/

rdnxtpge=rcvinfo;

if(rdnxtpge==PSTART)

WriteByte(idx,BNRY,PSTOP-1);

else

WriteByte(idx,BNRY,rdnxtpge-1);

return pktlength; 

The CPU writes the starting address of the network card send buffer and the number of bytes to be sent to RSAR[0,1] and RBCR[0,1] respectively through the remote DMA channel, and then starts the remote DMA write command to write the data packet into the network card memory. After that, the number of bytes is written to the TBCR[0,1] register and the send command is started to send the data packet to the network. The key code of the network card is as follows:

/*AX88796B_transmit*/

/*Write data to the network card's send buffer*/

WriteByte (RSAR0,0x00);

WriteByte (RSAR1,TX_BUF_Start);

WriteByte (RBCR0,(uint8)(len&0xFF));

WriteByte (RBCR1,(uint8)(len>>8));

WriteByte (CR,0x12); 

WriteData((uint16*)addr,len);

WriteByte (idx,TPSR,TX_BUF_Start); 

/*Send the data in the send buffer to the network*/

WriteByte (TBCR0,(uint8)(len&0xFF)); 

WriteByte (TBCR1,(uint8)(len>>8)); 

WriteByte (CR,0x26);

3 Interrupt processing

The processing of interrupts is closely related to the CPU. The chip select line and interrupt signal line of the network card must be configured in the software. When a data packet arrives, the network card saves it in SARM and triggers an interrupt at the same time. After the processor receives the interrupt signal, it enters the interrupt handler. In the interrupt handler, the interrupt status register ISR of AX88796B is read to determine the type of interrupt. If the lowest bit of the read value is 1, it means that the data packet is received interrupted. At this time, a message needs to be triggered to enter the read network card function. The function of the read network card function is to receive the network data packet from the memory of the network card to the host, and then pass it to the upper layer for corresponding processing.

The process of sending a message is to send the message to the memory of the network card by calling the write network card function. Then set the transmit bit TXP (Transmit packet) of the control register (CR) of AX88796 to 1, that is, to send the message.

The key code of the interrupt handling subroutine:

/*IRQ0_handler*/

uint8 InterruptStatus;

InterruptStatus=read(ISR);//Read the interrupt status register

write(IMR,0x00);//Disable interrupt

write(ISR,InterruptStatus);//Clear the interrupt status register

if(InterruptStatus&0x01)//Is it a data packet receiving interrupt

OSQPost(TcpIpMsgQ,&idx);//Notify the host computer that the data packet has been received

write(IMR,0x11);//Enable receiving interrupt and overwriting interrupt