ARM920T coprocessor CP15

The ARM920T processor contains the ARM9TDMI core, which implements the ARM architecture v4T. The








ARM920T processor contains two coprocessors:

CP14. Used for debugging

CP15. System control coprocessor, provides additional registers to configure and control cache, MMU, protection system, clock mode, and other system options of the ARM920T, such as big and small endian operation. You can use MCR, MRC to access the registers defined in CP15.

CP15 defines 16 registers, and the register mapping diagram is as follows:







Note: Register position 0 can access two registers, determined by the value of opcode_2.

ARM920T has 3 addresses.











CP15 can only be accessed in privileged mode using MCR and MRC instructions. The format of these instructions is:

MCR/MRC{cond} P15,,Rd,CRn,CRm, 

instructions CDP, LDC, STC and MRC, MCR instructions in non-privileged mode operate CP15 will cause undefined instruction exception. The CRn field of the MRC and MCR instructions specifies the coprocessor register to be accessed. The opcode_1, and CRm fields should be 0 unless a value is specified to select the desired operation.

Register 0, ID code register

can be set to any value except 1 by reading CP15 register 0. The opcode_2 field should be 0 (CRm should be 0 when reading).

For example:

MRC p15,0,Rd,c0,c0,0;return ID register







cache type register 0

contains information about the size and architecture of the cache. The cache type register can be accessed by setting the field to 1 and reading CP15 register 0. For example:

MRC p15,0,Rd,c0,c0,1;returns cache details







The Dsize and Isize fields have the same format:















Register 1, control register

This register contains the control bits for the ARM920T.

MRC p15,0,Rd,c1,c0,0 ;read control register

MCR p15,0,Rd,c1,c0,0;write control register











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Register 2, translation table base (TTB) register

This is the page table base register.







Use the following instructions to access the TTB:

MRC p15,0,Rd,c2,c0,0;read TTB register

MCR p15,0,Rd,c2,c0,0;write TTB register

Register 3,domain access control register

This is the read and write domain access control register.

















MRC p15,0,Rd,c3,c0,0;read domain 15:0 access permissions

MCR p15,0,Rd,c3,c0,0;write domain 15:0 access permissions

Register 4,reserved

Register 5,fault status registers

Register 6,fault address registers

Register 7,cache operations register







Register 8,TLB operations register

is used to manage Translation Lookaside Buffers (TLBs), instruction TLB and data TLB.







Register 9,cache lockdown register

opcode_2=0x0 accesses Dcache 

opcode_2=0x1 accesses Icache









Regiter 10,TLB lockdown register

opcode_2=0x0 accesses D TLB 

opcode_2=0x1 accesses I TLB







Register 11,12,and 14,reserved

Register 13,FCSE PID register

is the fast context switch extension register.








MRC p15,0,Rd,c13,c0,0;read FCSE_PID

MCR p15,0,Rd,c13,c0,0; write FCSE_PID

The addresses issued by ARM9TDMI in the range of 0 to 32MB are converted by register 13 of CP15. Address A becomes A+(FCSE_PID×32MB). FCSE_PID is a 7-bit field that enables 128×32MB of processes to be mapped.









Register 15,test configuration register