Design of orthogonal signal source filter based on single chip microcomputer

1 Introduction  

Since the traditional multi-waveform function signal generator requires a large number of discrete components to realize and the design is complex, a multi-waveform function signal generator based on CPLD is proposed here. It uses CPLD as the processor of the function signal generator, with the microcontroller and CPLD as the core, supplemented by necessary analog and digital circuits, to form a multifunctional function signal generator based on DDS (direct digital frequency synthesis) technology, with stable waveform and high precision.  

2 System Design  

Figure 1 shows the system design block diagram. The system design mainly consists of CPLD circuit, microcontroller circuit, keyboard input LCD display output circuit, D/A conversion circuit and low-pass filter circuit.  



2.1 Frequency synthesizer  

This system design adopts direct digital frequency synthesis DDS (Direct Digital Frequency Synthesis) technology, uses ROM to store the required quantization data, and calculates the frequency control word according to different frequencies. The phase accumulator is accumulated with K as the step. Each time it is accumulated, the high 8-bit data of the accumulator is taken out and sent to ROM. ROM takes out different data according to different addresses and sends them to TLC7524 for conversion. After filtering, the required waveform can be obtained. Since DDS has the advantages of relatively wide bandwidth, extremely short frequency conversion time, and high frequency resolution. In addition, the fully digital structure is easy to integrate, the output phase is continuous, and the frequency, phase and amplitude can all be program-controlled.  

2.2 Amplitude Control Module  

The amplitude control module is controlled by DAC0832, and its internal resistor voltage divider network is used as a digitally controlled potentiometer. The output waveform of TLC7524 is used as the reference voltage source input of DAC0832, and its output waveform is V=(N/256)×Vin, where N is the amplitude control word input by the microcontroller. Through a simple resistor voltage divider network, the peak-to-peak value of the op amp output is adjusted to 0~5 V, and then sent to DAC0832, where the microcontroller controls its amplitude to achieve amplitude stepping, as shown in Figure 2.  



2.3 The post-processing module  

uses a second-order Butterworth low-pass filter. The amplitude function of the Butterworth low-pass filter is monotonically decreasing. Since the first (2n-1)-order derivative of the n-order low-pass Butterworth low-pass filter is zero at ω=0, the Butterworth low-pass filter is also called the maximum flat amplitude filter. Since the frequency components required to be filtered out in this design are mainly high-frequency components generated by the D/A converter, which are far from the frequency required to be retained by the system, the flatness of the filter in the passband is more important than its attenuation steepness. In addition, the component values ​​required by the Butterworth low-pass filter are in line with the actual situation, unlike other filters that require component values.  

3 Hardware Circuit System Design  

3.1 Overall Design Idea  

The entire system is based on CPLD (EPM7128), AT89S51, and AT28C64 (EEP-ROM). CPLD generates the address for reading ROM through phase accumulation. The microcontroller is the core of the system control. Its main functions are: sending the frequency control word to the CPLD, that is, the accumulated value of the phase accumulator, to control the frequency; sending the amplitude control word D to the D/A converter to control the waveform amplitude; processing the infrared remote control keyboard; sending data to the LCD. The EEPROM stores the data of the solidified waveform.  

3.2 CPLD module  

This module is programmed in the system (ISP) through a 4-pin industrial standard JTAG interface, and only requires a single voltage of 5.0 V during the programming process. During the programming process, the I/O pins are in three states and pulled up to eliminate on-board conflicts. The pull-up resistance is 1 kΩ. Because the device is programmed online, in order to facilitate debugging, the download port is directly made on the circuit board. Considering that the power supply is a homemade voltage regulator, the CPLD is greatly affected by the power supply ripple interference, so a decoupling capacitor is added next to each device.  

3.3 D/A conversion and amplitude control  

The D/A conversion uses TI's TLC7524, which has a conversion speed of up to 10 M. The amplitude control D/A conversion uses MAX518, which is a dual D/A converter of the I2C bus. It only needs a few port lines to achieve two-way amplitude control, greatly saving the ports of the single-chip computer. Figure 3 shows the D/A conversion circuit. [page]



3.4 Post-processing module  

The low-pass filter performs Fourier analysis on the step sine wave. If the number of sampling points in one cycle is N, the high-order harmonic energy is mainly concentrated on the (N±1) times of the output frequency, and its amplitude is 1/(N±1) of the base frequency. The low-pass filter can smooth its steps. In addition, the high-frequency components of 1MHz and 10 MHz generated by DAC0832 and TCL7524 need to be filtered out. Therefore, according to the design requirements (the maximum output frequency is 250 kHz, in order to ensure the output amplitude is flat within the 250 kHz band, and to suppress harmonics and high-frequency components as much as possible, the broadband operational amplifier LF351 is selected after comprehensive consideration. The EWB simulation shows that the amplitude is flat within the cutoff frequency of 1 MHz to 250 kHz. In order to ensure stable output, AD817 is selected. This device is a low-power, high-speed, broadband operational amplifier with strong high-current driving capability. Actual circuit measurements show that when the load is 100 Ω and the output peak-to-peak value is 10 V, its bandwidth is greater than 500 kHz and the amplitude variation is less than ±1%.  

4 Software Design  

4.1 Waveform generation  

A 25-bit phase accumulator is set in the CPLD, with the upper 9 bits being the ROM address and the lower 16 bits being the ROM address. The accumulator register is set to generate the precise time interval between the points of reading ROM, that is, the single-chip microcomputer sends a frequency control word, and the low 16-bit register accumulates this value every clock, accumulates to the low 16-bit overflow, and then the ROM address is increased by 1. The data of each address in the ROM represents the amplitude of the current waveform, and then the data is read out continuously and smoothed and filtered to obtain a smooth and stable waveform. The waveform generation process is shown in Figure 4.  



4.2 Amplitude control  

system The amplitude control is completed by MAX518, and its internal resistor network is used to realize the digital potentiometer function. The output voltage is used as the reference voltage of TLC7524. Figure 5 is the amplitude control process. 



5 Circuit system debugging and parameter testing  

The instruments used for debugging and testing are PC, dual-trace analog oscilloscope YUAN-LONG, SS7200 universal intelligent counter, and DT9205 three-and-a-half-digital multimeter. The voltage amplitude is tested at a user 1 kHz step of 20 mV. Table 1 is the voltage amplitude test, and Table 2 is the output frequency test.  



6 Conclusion  

The frequency and amplitude of the DDS orthogonal signal source based on single-chip microcomputer and CPLD can be precisely controlled, the output frequency can be extended to 300 kHz, and the frequency sweep output function is added. The infrared keyboard is used to control the frequency and amplitude, and the LCD is used to synchronously display the frequency and amplitude of the signal; the output end generates sine wave, square wave, triangle wave, sawtooth wave, trapezoidal wave, short wave, square wave with frequency mutation, sharp pulse digital signal, etc., and has the function of frequency sweep output. The test results show that the system is stable and reliable, the human-computer interaction interface is friendly, and the operation is simple and convenient.