Detailed explanation of MSP430 system clock-EEWORLD

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After power-on reset, DCO is about 800KHz

The basic clock of SP430 series microcontrollers is mainly composed of low-frequency crystal oscillators, high-frequency crystal oscillators, digitally controlled oscillators (DCO), frequency-locked loops (FLL) and FLL+ modules. The clock modules will also be different due to the different models of 430 series microcontrollers. Although the time base modules of different models of microcontrollers are different, the results generated by these modules are the same. There is a TX2 oscillator in MSP430F13 and 14, while LFXT1CLK is used to replace the XT2CLK clock signal in MSP430F11X and F11. There are 3 (for F13 and F14) time signal sources (or 2 clock signal sources for F11X and F11X1) in the clock module:

1-LFXT1CLK: Low frequency/high frequency clock source. It is connected to an external crystal oscillator without the need for two external oscillation capacitors. The commonly used crystal oscillator is 32768HZ.

2-XT2CLK: High frequency clock source. It is an external crystal oscillator. Two external oscillation capacitors are required. The most common crystal oscillator is 8MHZ.

3-DCOCLK: Digitally controllable RC oscillator.

The default clock source for the microcontroller when it is powered on is the DCO clock, because as long as it is within the normal operating voltage, the DOC will provide a stable clock source.

After the PUC signal, DCOCLK is automatically selected as the MCLK clock signal. The clock source of MCLK can be set to LFXT1 or XT2 as needed. The setting sequence is as follows:

1. Reset OscOff

2. Clear OFIFG

3. Delay waiting for at least 50us

4. Check OFIFG again. If it is still set, repeat steps 3 and 4 until OFIFG = 0.

The MSP430 microcontroller clock module provides three clock signal outputs for use by various circuits within the chip.

1-ACLK: Auxiliary clock signal. As shown in the figure, ACLK is obtained by dividing the FLXT1CLK signal by 1/2/4/8 dividers. The division factor is determined by setting the DIVA corresponding to the BCSCTL1 register. ACLK can be used to provide CPU peripheral function modules as clock signals.

2-MCLK: Main clock signal. As shown in the figure, MCLK is provided by 3 clock sources. They are LFXT1CLK, XT2CLK (F13, F14, if it is F11, F11X1, it is replaced by LFXT1CLK), and DCO clock source signal. MCLK is mainly used as clock for MCU and related system modules. Related registers can also be set to determine the frequency division factor and related settings.

3-SMCLK: Subsystem clock, SMCLK is provided by 2 clock source signals. They are XT2CLK (F13, F14) and DCO. If it is F11, F11X1, LFXT1CLK will replace TX2CLK. You can also set the relevant registers to determine the frequency division factor and related settings.

Principle description of clock generator:

Problem: 1. High frequency, so as to respond quickly to system hardware requests and events

2. Low frequency to minimize current consumption

3. Stable frequency to meet the application of timer.

4. Low Q value oscillator to ensure no delay in starting or stopping operation

MSP430 adopts a compromise method: using a low-frequency crystal oscillator to multiply it to a high-frequency operating frequency. Generally, there are two practical methods to use this technology, one is the phase-locked loop, and the other is the frequency-locked loop. The phase-locked loop uses analog control, which is easy to cause "loss of lock" and change in capacitance. TI uses the frequency-locked loop technology, which uses a digital controller DCO and frequency integration to generate a high-frequency operating clock frequency.

Tips for low power settings:

1. LPM4: During the oscillator shutdown mode, all parts of the processor stop working, and the current consumption is minimal. At this time, it will only work again when the system power-on circuit detects a low level or any external interrupt event that requests an asynchronous response interrupt. Therefore, the design should include external interrupts that may be needed to use this mode. Otherwise, unpredictable results may occur.

2. LPM3: During the DC generator shutdown period, only the crystal oscillator is active. However, the DC current of the DC generator that sets the basic timing conditions is turned off. Due to the high-impedance design of this circuit, power consumption is suppressed. Note: It takes a certain amount of time (ns-us) from DC shutdown to DC0 startup

3. LPM2: During this period, the crystal oscillator and DC generator are working, so a quick start can be achieved.

4. LPM1: The oscillator is already working here, so there is no startup time delay problem.

In combination with the above characteristics, when writing programs, you must comprehensively consider the low power consumption characteristics, and the arrangement of external events is also very important. You must comprehensively consider the function implementation to achieve your expected effect. Using C language, you can use the following statements: _BIS_SR (LMP3_bits) and _BIC_SR (LPM3 bits)

#include

#include "BoardConfig.h"

void DelayMs(unsigned int ms)

{

unsigned int i;

while(--ms)

{

for(i=110;i>0;--i);

}

void main(void)

{

volatile unsigned int i;

BoardConfig(0xb0);

WDTCTL = WDTPW + WDTHOLD; // Stop WDT

P5DIR |= 0x10; // P5.4= output direction

P5SEL |= 0x10; // P5.4= MCLK option select

BCSCTL1 &= ~XT2OFF; // XT2= HF XTAL

P2DIR |= 0xff;

{

IFG1 &= ~OFIFG; // Clear OSCFault flag Clear oscillator failure flag

for (i = 0xFF; i > 0; i--); // Time for flag to set

}

while ((IFG1 & OFIFG)); // OSCFault flag still set? Using an external clock will be much faster

BCSCTL2 |= SELM_2; // MCLK= XT2 (safe)

for (;;) // Do nothing

{

P2OUT = ~P2OUT;

DelayMs(10000); // Using an external clock will be much faster

}

Keywords：MSP430 Reference address：Detailed explanation of MSP430 system clock

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