Design of a new grating digital display system based on MCU+CPLD

　　Grating digital display systems are mainly used for ordinary machine tools. They can directly display the length value of machine tool processing, which helps to improve processing accuracy and efficiency. At present, most of the grating digital display systems on the domestic market are implemented with foreign integrated circuits, which have high R&D costs and are not convenient for operators to use. In response to this situation, a new grating digital display system based on MCU+CPLD has been developed. The system has the characteristics of high counting accuracy, low cost, convenient operation and fast upgrade. It can process orthogonal pulses up to 5 MHz/s and effectively store the current length value when power is off. Its digital tube can display the key length value, and the dot matrix LCD screen can also display relevant prompt information.

　　2 System Working Principle

　　CPLD is used to implement the orthogonal pulse processing logic circuit, and the reversible counter is used to process the orthogonal pulses output by the counting grating ruler. The high-speed parallel processing capability of CPLD can ensure that the output signal of the grating ruler is sampled without omission, thereby ensuring the reliability of counting. The value of the reversible counter is converted into the length value processed by the machine tool after a series of operations by the MCU, and the MCU then sends its length value back to the CPLD and displays it on the digital tube.

　　In addition, the CPLD also has the function of 7×8 keyboard key detection and debounce, and sends the processed reliable keys to the MCU. The MCU is mainly used for LCD display control, power-off data storage, and complex mathematical operations. The system working principle block diagram is shown in Figure 1.

　　3. Orthogonal pulse signal acquisition and processing

　　3.1 Orthogonal pulse acquisition

　　The grating ruler outputs a set of orthogonal pulse signals, that is, two square waves with a phase difference of 90°, as shown in Figure 2. When the grating ruler moves one grating pitch in the forward direction, the grating ruler outputs a 00-01-11-10-00 cycle, and the phase of square wave A leads that of square wave B by 90°; when the grating ruler moves one grating pitch in the reverse direction, the grating sensor outputs a 00-10-11-01-00 cycle, and the phase of square wave A lags that of square wave B by 90°.

　　By analyzing the logic states of square waves A and B, it is found that only one signal of the two square waves A and B changes its logic state at any time. If the states of A and B are the same before the change of logic state, then the logic states after the change must be different; if the logic states of A and B square waves are different before the change, then the logic states after the change must be the same. By simply XORing these two signals, the direction signal updown of the grating ruler movement and the counting pulse cp proportional to the movement distance can be extracted.

　　As shown in Figure 2, when the grating ruler moves one pitch, it will output 4 cp pulses, and the minimum resolution of the system measurement is increased to 1/4 pitch, which is usually called four-splitting phase or four-fold frequency. The CPLD detects the state of the two square waves A and B at the rising edge of each clk. First, the current detected state A0, B0 and the last detected state A1, B1 are XORed, and then the two XOR values ​​are XORed again. If the final XOR value is 1, it means that the two square waves A and B have changed, and a counting pulse cp with a high level width of 1 clk cycle is input to the reversible counter. The implementation logic is shown in Figure 3.

　　3.2 Reversible Counter

　　The extracted direction signal updown and count pulse cp are input into the reversible counter to count the orthogonal pulses output by the grating ruler. The VHDL program of the reversible counter module is as follows:

　　3.3 clk value

　　Since the sampling clock clk of the CPLD must be greater than the orthogonal pulse output by the 8-fold grating ruler, the system will not lose the signal. The system is designed to use a 40 MHz active crystal oscillator as the sampling clock source of the CPLD, and the maximum grating sensor output signal frequency that can be recorded is 5 MHz. If a 50-line/mm grating ruler is used, after the four-phase subdivision of the CPLD, the maximum non-missing processing speed of the grating ruler connected to the system is calculated to be 20 μm×5 MHz=100 m/s, and the minimum resolution is 5 μm. This is far beyond the limit speed of the machine tool operation and fully meets the actual needs.

　　3.4 Introduction to EPM240

　　Altera's EPM240 is selected as the CPLD, which is a member of the MAX II series. The architecture of the MAX II CPLD series makes it the lowest power consumption and cost per I/O pin among all CPLD series devices; it supports internal clock frequencies up to 300 MHz and is targeted at general low-density logic applications. MAX II CPLD can replace high-power and high-cost ASSPs and standard logic CPLDs.

　　EPM240 contains 240 logic units (LE), equivalent to 192 macro units; 8 192-bit user Flash memory can meet the user's small-capacity information storage requirements; the maximum number of user I/Os is 80, and the fastest speed is 4.5 ns, which fully meets the system design requirements. [page]

　　4 MCU power-off data storage

　　Power-off data storage is another important function of system design, which requires high reliability. The system should save the current position information of the grating ruler when the power is off, and restore the system by calling the position information saved when the power is off the next time. Therefore, at the moment of power off, the power off alarm circuit will respond quickly and send an alarm signal to the MCU; after the MCU detects the alarm signal, it will immediately perform corresponding processing and store the current position information of the grating ruler in the EEPROM. Its hardware circuit is shown in Figure 4.

　　In order to improve the power-off response speed of the MCU and enhance system reliability, the system design uses the new enhanced 51 microcontroller STC-89C516RD. This device has 1 KB RAM and up to 64 KB large-capacity ROM, ISP function, and two optional modes of instruction cycle: 6clock and 12clock. Using a 20 MHz crystal oscillator, when programming in 6clock mode, the program execution time of a single instruction cycle is only 0.3μs, which is much faster than the running speed of ordinary 51 microcontrollers under the highest 24 MHz crystal oscillator. Therefore, the execution time of the power-off data storage program is greatly shortened.

　　4.1 Power-off alarm circuit

　　The ultra-small high-precision voltage detector S80848 is selected. The internal detection voltage is fixed at 4.8 V, the accuracy is ±2%, and the maximum response time is 60μs. The S80848 uses a standard 5 V power supply. When the power supply is normal, it outputs a high level; when the power supply voltage drops to 4.8 V, it outputs a low level. Connect the output pin of the S80848 to the INT0 of the MCU, and set the INT0 of the MCU to level trigger. Therefore, as long as the power supply voltage is lower than 4.8 V, the MCU will enter the INT0 interrupt, and the MCU saves the position information in the interrupt program.

　　4.2 EEPROM selection

　　When the MCU completes the write operation to the EEPROM, the EEPROM needs a maximum self-write time of 10 ms to write the information to the storage unit. In order to use more time for EEPROM self-write, a low-voltage EEPROM, namely AT24C64-2.7 V, is selected. Its operating voltage is 5.5 V ~ 2.7 V, the capacity is 64 KB, each page is 32 B, and the maximum number of writes is 1 000 000.

　　4.3 Power-off time calculation

　　The STC89C516RD with an operating voltage of 4.5 V to 5.5 V is selected. When the power supply voltage drops below 4.5 V, the MCU cannot work reliably. The interrupt service program of INT0 of the MCU can only use the period when the power supply voltage drops from 4.8 V to 4.5 V, and all processing must be completed within this period. Therefore, when designing the interrupt program, we should try to consider the shortest execution time. The interrupt should first store all stored data in an array, and then write all elements of the array to AT24C64. Of course, the number of elements in the array must be less than the length of one page of AT24C64, that is, it must be less than 32 B.

　　When the output voltage is 5 V, the maximum current is Imax = 0.8 A, the equivalent load is R = 5 / I = 6.25 Ω, and the capacitor C = 4 700 μF in parallel with the 5 V power supply, then the system time constant is τ = RC = 0.029 s. Assuming that power failure occurs at t = 0, according to the formula u(t) = Vccexp(-t / τ) = 5exp(-t / 0.029), it can be seen that: at t = 1 183 μs, the power supply voltage Vcc drops from 5 V to 4.8 V; at t = 3 055 μs, Vcc drops to 4.5 V; at t = 17 869 μs, Vcc drops to 2.7 V. The interrupt service program time of MCU is 3 055-1 183=1872μs, which is greater than the measured interrupt service program time 1 350μs; the EEPROM self-write effective time is 17 869-3 055=14 814μs, so it fully meets the EEPROM write requirements.

　　4.4 Interrupt Service Routine

　　In order to prevent the MCU from frequently writing to the EEPROM and the number of times used exceeds the maximum valid writing number, the interrupt program performs necessary filtering on the level of the interrupt input pin. The filtering algorithm is: after the system enters the interrupt program, it first turns off the interrupt, and then judges the level of INT0 for 10 consecutive times. If the level value obtained each time is low, the interrupt service program will continue to be executed. As long as there is a high level, the interrupt service program will be exited immediately. After completing the data writing, make sure that the low level on INT0 is released before returning to the interrupt, otherwise wait until the low level is released. The flow chart of the interrupt service program is shown in Figure 5.

　　5 Conclusion

　　The design of the grating digital display system is introduced in detail. The use of CPLD can greatly simplify the system hardware design, reduce system costs, and enhance system reliability and flexibility. The selection of STC89C516RD can avoid the expansion of external memory, thereby simplifying the peripheral circuit design of the single-chip microcomputer.