Issues that must be noted when using MSP430F1121 interrupts

　　MSP430F1121 (hereinafter referred to as F1121) is a cheap 20-pin low-power 16-bit Flash microcontroller recently launched by TI. Its multiple interrupt functions make it flexible and suitable for various application fields.

　　However, we found in the application development that although there are many technical documents provided by the manufacturer, the description of interrupts is not so detailed, which caused many inconveniences to the application development. For this reason, we conducted some experiments with the program and clarified some problems. Here, we will explain these problems for your reference.

　　Before explaining these issues, it is necessary to look at the interrupts of F1121, as listed in Table 1.

　　Table 1 F1121 interrupt

　　Each interrupt of F1121 has a corresponding interrupt vector and interrupt priority, which are usually divided into three categories: system reset, (non-) maskable interrupt and maskable interrupt. In addition, each interrupt of F1121 is divided into single-source interrupt and multi-source interrupt, and the corresponding interrupt flags are called single-source interrupt flag and multi-source interrupt flag.

　　1. System reset

　　Formally speaking, system reset can be regarded as an interrupt, but it is a special interrupt. Although it also has an interrupt vector (reset vector) and interrupt priority, it is significantly different from interrupts in the usual sense: system reset causes the system to enter the initial state and forces the program to run from the beginning.

　　1. Situations that cause system reset and POR and PUC signals

　　There are four situations that can cause the system to reset and generate POR (Power-On Reset) and PUC (Power-Up Clear) signals:

　　Power-on reset – generates POR and PUC;

　　· RST reset (external reset signal reset) – generates POR and PUC;

　　Watchdog interrupt – only generates PUC;

　　· Key Error Interrupt – Generates PUC only.

　　POR and PUC are both internal chip signals generated when the system is reset, responsible for initializing the registers. In the technical documents provided by F1121, the initial states of the register bits that are initialized by the PUC signal are represented by "0" and "1", while those that are initialized by the POR signal are represented by "(0)" and "(1)". For example, in the BCSCTL1 register shown in Figure 1, the upper 4 bits are initialized by the POR, and the lower 4 bits are initialized by the PUC.

　　Different system reset situations generate different PUC and POR, and thus different system initialization results. For example, for the BCSCTL1 register, no matter what causes the system reset, its lower 4 bits will return to the initial state; the upper 4 bits will only return to the initial state in the two cases of power-on reset and RST reset, and in other cases (unless the chip is powered off), its state remains unchanged.

　　2. Watchdog interrupt flag WDTIFG

　　The watchdog timer has two working modes, and both use the interrupt flag WDTIFG, but their performance is significantly different. In the watchdog working mode (generating a watchdog interrupt that causes a system reset), it behaves as follows: When a watchdog interrupt occurs and causes a system reset, WDTIFG will be set to "1" ("0" in other reset situations). At this time, WDTIFG cannot be automatically cleared to "0", and can only wait for the software (program instructions) to clear it to "0". However, even if it is not cleared to "0" (regardless of whether WDTIFG is "1" or "0"), it will not affect the operation of the program, and it will not prevent the watchdog interrupt from being generated again. In fact, at this time, WDTIFG only serves to mark whether a watchdog interrupt has occurred in order to distinguish the cause of the system reset. The same is true for the interrupt flag KEYV of another key code error interrupt that causes a system reset.

　　In addition, the interrupt enable bit WDTIE has no effect on the watchdog interrupt.

　　2. Interruption

　　Interrupts are divided into maskable interrupts and non-maskable interrupts. The only criterion for distinguishing them is whether GIE (general control bit for maskable interrupt enable) can disable the interrupt. Any interrupt that can be disabled by GIE is a maskable interrupt, and any interrupt that cannot be disabled is a non-maskable interrupt.

　　But in F1121, the real non-maskable interrupts are only watchdog interrupt and key code error interrupt. These two interrupts are not ordinary interrupts because they will cause system reset. In addition, there are three other interrupts that belong to the category of non-maskable interrupts, but they are not real non-maskable interrupts because they each have their own interrupt enable control bits, which can mask their interrupts. Therefore, these three interrupts are represented by "(non) maskable interrupts".

　　1. Interrupt flag

　　Both maskable interrupts and (non-) maskable interrupts have their own interrupt flags, and their common characteristics are: ① The state of the interrupt flag has nothing to do with whether the interrupt source can generate an interrupt. In other words, regardless of whether the interrupt is allowed, as long as the interrupt condition is met, the interrupt flag will be set to "1". In addition, the interrupt flag can also be set to "1" or cleared to "0" by software. ② The interrupt source requests an interrupt through the interrupt flag (when the interrupt is allowed). The following takes the (watchdog) timer interrupt (unlike the watchdog interrupt, it generates a maskable interrupt, the interrupt vector is FFF4h, and the interrupt priority is 10) as an example to illustrate.

　　· When the interrupt is enabled, an interrupt will be generated regardless of the reason as long as WDTIFG is set to "1". For example, a timer overflow (WDTIFG is set to "1" at this time) will generate an interrupt, and forcibly setting WDTIFG to "1" by software will also generate an interrupt.

　　If WDTIFG is set to “1” when interrupts are disabled, it will generate an interrupt once enabled.

　　If WDTIFG is set to "1" when interrupts are disabled, but it is cleared to "0" before enabling interrupts, then it will not generate an interrupt even if it is enabled.

　　There are two types of interrupt flags - single-source interrupt flags and multi-source interrupt flags, which have different characteristics.

　　(1) Single source interrupt flag

　　If an interrupt vector (that is, an interrupt handler) corresponds to only one interrupt source, then this interrupt is called a single-source interrupt, and its interrupt flag is the single-source interrupt flag. For example, WDTIFG of the (watchdog) timer interrupt, CAIFG of the comparator A interrupt, and CCIFG0 of the timer A interrupt are all single-source interrupt flags.

　　The characteristic of the single-source interrupt flag is that when the single-source interrupt is responded to, its single-source interrupt flag will be automatically cleared to "0".

　　However, please note that if the single-source interrupt flag is set to "1" again during the interrupt processing (before the interrupt returns), it will not be automatically cleared to "0" and can only be cleared to "0" by software.

　　(2) Multi-source interrupt flag

　　If an interrupt vector corresponds to multiple interrupt sources (that is, multiple interrupts share one interrupt handler), then these interrupts are called multi-source interrupts, and the corresponding interrupt flags are multi-source interrupt flags. For example, the three (non-) maskable interrupts NMIIFG, OFIFG, ACCVIFG and the timer A interrupt CCIFG1, CCIFG2, TAIFG and all interrupt flags of P1 and P2 ports are multi-source interrupt flags.

　　The characteristic of multi-source interrupt flag is: when multi-source interrupt is responded, multi-source interrupt flag cannot be automatically cleared to "0", and can only be cleared to "0" by software. Therefore, do not forget to clear the multi-source interrupt flag to "0" before the interrupt returns; otherwise, when the interrupt returns, the interrupt flag that has not been cleared to "0" will immediately request an interrupt again.

　　2. (Non-)maskable interrupts

　　There are three (non) maskable interrupts: NMI interrupt, oscillator fault interrupt and Flash read/write error interrupt. They are not affected by the GIE state, but each has an interrupt enable bit: NMIIE, OFIE and ACCVIE. Only when the interrupt enable bit is set, the corresponding interrupt source can be allowed to generate an interrupt.

　　Note: For these three (non-) maskable interrupts, once one of them is responded to, all three interrupt enable bits will be automatically reset and remain in the reset state. Even after the interrupt returns, they will not automatically restore to the previous state, so they need to be reset by software. In addition, it should be noted that these three interrupts are multi-source interrupts.

　　3. Maskable interrupts and GIE

　　Interrupts that can be disabled by GIE are maskable interrupts, some of which are single-source interrupts (single-source interrupt flags) and some of which are multi-source interrupts (multi-source interrupt flags). All of these interrupts have their own interrupt enable bits. Only when the interrupt enable bit is set and GIE is set, can the corresponding interrupt source be allowed to generate an interrupt. Except for system reset or rewriting by software, any other situation (including interrupt response or interrupt return, etc.) will not affect the status of these interrupt enable bits.

　　GIE is the maskable interrupt enable general control bit. When it is reset, all maskable interrupt sources are prohibited from requesting interrupts. When it is set, they may be allowed to request interrupts (whether it can be allowed depends on the status of their respective interrupt enable bits).

　　Note: When any interrupt is responded to, including maskable interrupts and (non-) maskable interrupts, GIE will be automatically reset; when the interrupt returns, it will automatically restore to its pre-interrupt state (unless the contents of GIE saved in the stack are overwritten during interrupt processing).

　　If the reset GIE is reset by software during interrupt processing, a maskable interrupt nest can be formed.

　　4. Interrupt Priority

　　The interrupt priority of F1121 is slightly different from the concept in other microprocessors: it is only valid for the situation where multiple interrupts occur at the same time (interrupts with higher levels are responded to first), and there is no restriction on the situation of nested interrupts.

　　5. Interrupt nesting

　　If another interrupt request is responded to during the processing of a certain interrupt, interrupt nesting will be formed. When interrupts are nested, the processing of the previous interrupt is suspended, and the previous interrupt will be processed only after the next interrupt is processed.

　　Note: Maskable interrupts can only be embedded in the processing of this interrupt if GIE is reset during interrupt processing; however, (non-)maskable interrupts are not subject to this restriction and can be embedded in any processing at any time (if their interrupts are allowed). In addition, the interrupt nesting of F1121 is not subject to any restrictions on interrupt priority. In other words, high-level interrupts can be embedded in the processing of low-level interrupts; conversely, low-level interrupts can also be embedded in the processing of high-level interrupts, and can even form their own nesting. These situations are no exception for (non-)maskable interrupts. Therefore, special attention must be paid to this point when using F1121. Even if interrupt nesting is not intended, this issue must be considered because there is still the possibility of interrupt nesting, and if the nesting affects one (some) states of the interrupt, it may cause system operation errors.