In-depth analysis of the storage space structure of 8051 single-chip microcomputer

　　introduction

　　The single-chip microcomputer has a broad market prospect due to its cheapness, small size, strong plasticity and high stability. When developing products with switching power module single-chip microcomputers, although many manufacturers have designed programmable ISP single-chip microcomputers, single-chip microcomputer simulators are still indispensable tools for developers from the perspective of safety and convenience. Single-chip microcomputer simulators can be used to replace MTD2002 single-chip microcomputers for software and hardware debugging during the product development stage, so as to quickly discover and correct errors in the program, greatly shortening the development cycle of switching power module single-chip microcomputers. However, in practice, simulators are too expensive, so designing and producing a cheap and practical MTD2002 simulator has a broad market.

　　There are generally three ways to implement the hardware system of the traditional switching power supply module single-chip emulator. 1. Use a dedicated emulation single-chip microcomputer. 2. Use two sets of single-chip microcomputers, one single-chip microcomputer is used for emulation and completes functions such as communication and interruption; the other single-chip microcomputer is used for the target single-chip microcomputer, so that its resources will not be occupied. 3. Use the target single-chip microcomputer as an emulator. The single-chip microcomputer, that is, the emulator, is also used as the single-chip microcomputer of the target machine. In essence, it is a ROM monitor. The third method will occupy some resources of the single-chip microcomputer, but the structure is simple. For specific developers, it is practical, cost-effective, and easy to make by themselves. The emulator developed and designed in this article is based on the third principle, which cleverly realizes the interchange of data space and program space, and designs a practical and inexpensive emulator with strong engineering practice.

　　Principle and system structure

　　When the emulator is working, the program must be downloaded from the switching power supply module PC to the memory of the emulator. Here, the memory structure and addressing method of the 51 single chip are analyzed in detail, and then the expansion of the off-chip memory is analyzed. Finally, the design principle is given and the system structure is analyzed.

　　Figure 1 Storage space distribution

　　Analysis of 51 MCU memory structure

　　The memory of the 8051 microcontroller in the switching power supply module is physically divided into program memory space and data memory space, with a total of 4 storage spaces: MTD2002 on-chip program memory, off-chip program memory, on-chip data memory, and off-chip data memory space. This structure in which program storage and data storage are separated is called Harvard structure. However, from the user's perspective, the 8051 memory address space can be divided into 3 categories: 64KB program memory address space (using 16-bit address) with unified addressing of 0000H~FFFFH on-chip and off-chip; 64KB off-chip data memory address space, also addressed from 0000H~FFFFH (using 16-bit address); 256B on-chip data memory address space (using 8-bit address).

　　The addresses of the above four storage spaces overlap, as shown in Figure 1. The instruction system of 8051 has designed different data transfer instructions to distinguish these four different logical spaces: the CPU uses MOVC to access the on-chip and off-chip ROM instructions, MOVX to access the off-chip RAM instructions, and MOV to access the on-chip RAM instructions.

　　The program memory is used to store the compiled programs and table constants. The program is addressed by the 16-bit program counter, with an addressing capacity of 64KB. This allows instructions to jump arbitrarily within the 64KB address space, but cannot transfer the program from the program memory space to the data memory space.

　　In fact, when pin EA is connected to a high level, the program counter PC of the switching power supply module 8051 executes the program in the on-chip ROM. When the instruction address exceeds the on-chip ROM address, it automatically turns to the off-chip ROM to fetch instructions. When pin EA is connected to a low level (grounded), the on-chip ROM of 8051 does not work, and the CPU can only fetch instructions from the off-chip ROM. The address can be addressed starting from 0000H. The execution speed of 8051 is the same when fetching instructions from the on-chip program memory and the off-chip program memory.

　　Memory expansion

　　Using the P0 port as the address/data multiplexing bus and the P2 port line as the high-order address line, the memory of the switching power supply module can be expanded to 64KB at most. The control signal lines include: using ALE as the address latch selection signal to achieve the latching of the low 8-bit address; using the PSEN signal as the read selection signal for the extended program memory; using the EA signal as the selection signal for the internal and external program memory; using EA and as the read and write selection signals for the extended data memory and I/O port. When executing the MOVX instruction, the RD and WR signals are automatically valid respectively. The reading and writing of the off-chip data memory RAM are controlled by the RD (P3.7) and WR (P3.6) signals of the 8051, while the output enable (OE) of the off-chip program memory is controlled by the read selection PSEN signal. Although the off-chip data memory and the off-chip program memory are in the same address space, there will be no bus conflict due to the different control signals and data transfer instructions used.

　　Figure 2 Simulator schematic diagram

　　Simulator Principle and Structure

　　Since almost all MCUs with 8051 as the core now have internal FLASH program memory. For example, the switching power supply modules AT89C51 or AT89S51 used in this design have 4KB FLASH program memory, and some MCUs have 20KB or even larger program memory. Therefore, in the development of MCUs, it is rare to use special program memory chips to expand external program memory, and it is usually not necessary. Based on the above factors, the principle of the MTD2002 emulator implementation in this article is analyzed below.

　　When downloading the program, EA is connected to a high level, the microcontroller executes the program in the internal ROM, and downloads the program data of the PC to the off-chip RAM62256; when the program data is downloaded, while keeping the RAM62256 powered on, connect the EA of the microcontroller to a low level and reset the microcontroller. In this way, the microcontroller can only read data from the off-chip memory. Then use RD and PSEN to select the read enable chip select terminal OE of RAM62256, so that the microcontroller can read the program from RAM62256. In this way, the simulation function is realized. Because the execution speed of the microcontroller when fetching instructions from the on-chip program memory and the off-chip program memory is the same, the performance of the emulator under this design scheme is not inferior to the traditional emulator.

　　The overall system circuit principle is shown in Figure 2. The system consists of a single-chip microcomputer AT89C51, an address latch 74LS373, an off-chip memory 62256, an interface level conversion chip MAX232 and related control circuits.

　　Among them, AT89C51 is the core component of the emulator, and the crystal oscillator circuit and reset circuit are the same as those of ordinary single-chip microcomputer systems. The difference is that the switching power supply module EA is connected to a single-pole double-throw switch, and there is no extended ROM on the surface. The connection method of RAM62256 and OE is different from that of ordinary single-chip microcomputer systems. In the system, RD and PSEN are "ANDed" to enable the read enable chip select terminal OE of RAM62256, which can facilitate the RAM (note: RAM does not lose power during the whole process) to change from the role of data space to the role of program space. When executing the MOVX instruction, RD and WR signals are generated to write program information. When executing the program in RAM, the PSEN signal and RD signal select the OE terminal of RAM62256 to realize the reading of the program from RAM62256.

　　Software Design

　　The PC (host computer) software can refer to relevant books such as Windows driver development, serial port debugging MTD2002 assistant, etc.; it can also be completed using the existing Windows integrated development environment ~VISION51 and software simulator DSCOPE51 of the switching power supply module KEIL C51.

　　The main task of the lower computer software is to set up the serial port and receive data sent by the upper computer serial port, and store the data in the external "data" memory.

　　The main program of the microcontroller is as follows:

　　MOV SCON,#50H ;Serial port mode 1

　　MOV TMOD,#20H ;T1 mode 1

　　MOV TL1,#0FDH ; constant for baud rate 9600

　　MOV TH1,#0FDH

　　SETB TR1 ; Enable interrupt

　　SETB ET1

　　SETB ES

　　SETB EA

　　The system "writes" with the following command:

　　MOVX @DPTR,A

　　MOVX@Ri, A

　　In the interrupt service subroutine, in order to distinguish whether the received signal is a communication signal or a byte number, data or a checksum, different flag bits need to be set as follows:

　　FLAG0 BIT 00H ; Receive contact signal flag

　　FLAG1 BIT 01H ; Received byte number flag

　　FLAG2 BIT 02H ;Receive data flag

　　FLAG3 BIT 03H ; receive file end flag

　　The program flow is shown in Figure 3, where R7 is the number of bytes received. The received data must be stored in the unit of the switching power supply module's off-chip RAM starting from 0000H. When the MTD2002 microcontroller is reset and the RAM is used as a program memory, the PC starts from 0000H.

　　Figure 3 MCU receiving interrupt service subroutine flow chart

　　Some Discussions

　　(1) No separate emulator power supply or crystal oscillator circuit is required in the system.

　　(2) The external memory of the switching power supply module of the lower computer does not need to be erased when repeatedly writing data. Each time the program is re-downloaded, it is always overwritten. The newly downloaded program ends with END. Even if the newly downloaded program is shorter than the original one, no redundant code will be executed.

　　(3) In practice, the circuit can be further improved. After the file is downloaded, a control signal is generated through the spare signal line of the serial port to control and reset it, so that the entire process is controlled by the host computer.

　　(4) Due to the limitation of internal structure, the simulated product cannot expand the program memory outside the chip. However, since the data memory can be expanded to 64KB outside the chip, and only 32KB is used in this paper, certain peripherals can be expanded.

　　(5) The connection method of E(--)A(--) of the simulated product has certain restrictions. It cannot be directly connected to the ground or the positive pole of the power supply. In practice, just add a suitable MTD2002 current limiting resistor (such as 10K?). In fact, this solution can be applied to any microcontroller that can expand external memory.

　　Conclusion

　　It is not difficult to find that the technology of each functional module of the entire MTD2002 system is very mature by analyzing the above switching power supply module design: in terms of hardware, each sub-circuit has an existing circuit application, and the parameters of each component are easy to determine; in terms of software, it only involves the serial communication program of the COM port of the switching power supply module and the interface program of the host computer. In the actual MTD2002 production process, the system has a small number of components and low prices, is easy to debug, has a high success rate, and has stable performance.