51 MCU timer interrupt (register)

Interrupts are set up to enable the microcontroller to handle external or internal random events. The 51 microcontroller has 5 interrupt sources, that is, when there are 5 corresponding situations, the microcontroller will process the interrupt program (interrupt function).

This article mainly organizes the notes on timer interrupts. Using timer interrupts will involve knowledge points such as interrupt registers, timer/counter related registers (TCON, TMOD), interrupt functions, etc.

Among them, the interrupt register, the timer/counter related register itself or the related bit is used for initialization, and the content of the interrupt function mainly reflects the operation required after the interrupt occurs (writing code in the interrupt function).

1. Interrupt enable register IE

Figure 1. Interrupt register IE

The interrupt register is used to set the opening and closing of each interrupt source. The IE in the special function register has a byte address of A8H and a bit address (from low to high) of A8H~AFH. This register operates bit addressing, and each bit of the register can be operated separately. When the microcontroller is reset, all IEs are cleared. The following lists the specific meanings of each bit in different states:

EA-------Global interrupt enable bit

EA = 1, turn on the global interrupt control. Under this condition, each interrupt control bit (TRn bit in the TCON register) controls the opening and closing of the corresponding interrupt.

EA = 0, turn off all interrupts.

-- Invalid bit

ET2--Timer/Counter 2 Interrupt Enable Bit

ET2 = 1, turn on T2 interrupt.

ET2 = 0, turn off T2 interrupt.

ES--Serial port interrupt enable bit

ES = 1, turn on serial port interrupt.

ES = 0, turn off serial port interrupt.

ET1--Timer/Counter Interrupt Enable Bit

ET1 = 1, turn on T1 interrupt.

ET1 = 0, disable T1 interrupt.

EX1--External interrupt 1 interrupt enable bit

EX1 = 1, turn on external interrupt 1 interrupt.

EX1 = 0, turn off external interrupt 1.

ET0--Timer/Counter 0 interrupt enable bit

ET0 = 1, turn on T0 interrupt.

ET0 = 0, turn off T0 interrupt.

EX--External interrupt 0 interrupt enable bit

EX0 = 1, turn on external interrupt 0 interrupt.

EX0 = 0, disable external interrupt 0.

2. Timer/Counter Related Registers (TMOD, TCON)

Timer/Counter Operation Mode Register (TMOD)

Figure 2. Timer/Counter Operation Mode Register

The timer/counter working mode register is in the special function register, the byte address is 89H, and it cannot be bit-addressed. TMOD is used to determine the working mode and function selection of the timer. When the microcontroller is reset, TMOD is cleared to zero. The following describes the meaning of each bit under different values:

GATE --gate control bit.

GATE = 0, the start and stop of the timer/counter is only controlled by TRn (n = 0, 1) in the TCON register.

GATE = 1, the start and stop of the timer/counter are controlled by TRn (n=0, 1) in the TCON register and the level status of the external interrupt pin (INT0 or INT1).

C/T`--Timer mode and counter mode selection bit.

C/T` = 1, it is counter mode; C/T` = 0, it is timer mode.

M1M0--Working mode selection bit (see the table below)

Figure 3. Four modes of operation of a timer/counter

Timer/Counter Control Register TCON

The timer/counter control register is in the special function register, the byte address is 88H, the bit address (from low to high) is 88H~8FH, and the register can be bit-addressed. The TCON register is used to control the start and stop of the timer, flag register overflow and interrupt. When the microcontroller is reset, TCON is cleared to zero. The meaning of each bit being assigned different values ​​is as follows:

Figure 4. Timer/Counter Control Register TCON

TF1--Timer 1 overflow flag

When timer 1 overflows, the hardware sets TF1 to 1 and requests an interrupt. After entering the interrupt routine, the hardware automatically clears it to zero. If the timer interrupt is used, this bit does not need to be manually operated; but if the software query method is used, when the bit is found to be 1, it needs to be cleared by software.

TR1--Timer 1 run control bit

Timer 1 is turned off by software clearing it to 0. When GATE = 1 and INT1 is high, TR1 is set to 1 to start Timer 1; when GATE = 0, TR1 is set to 1 to start Timer 1.

TF0--Timer 0 overflow flag, its function and operation are the same as TF1.

TR0--Timer 0 running flag, its function and operation are the same as TR1.

IE1--External interrupt 1 request flag

When IT1 = 0, it is a level-triggered mode, and S5P2 samples the INT1 pin in each machine cycle; if the INT1 pin is at a low level, it is set to 1, otherwise IE1 is cleared to 0.

When IT1 = 1, INT1 is in edge trigger mode. When INT1 is sampled as low level in the first machine cycle, IE1 is set to 1. When IE1 = 1, it means that external interrupt 1 is requesting an interrupt from the CPU. When the CPU responds to the interrupt and turns to the interrupt service routine, this bit is cleared to 0 by hardware.

IT1--External interrupt 1 trigger mode selection bit

IT1= 0, which is level trigger mode, and the low level on pin INT1 is valid.

IT1 = 1, which is the transition edge trigger mode. The negative transition of the level on pin INT1 from high to low is valid.

IE0--external interrupt 0 request flag, its function and operation are the same as IE1.

IT0--External interrupt 0 trigger mode selection bit, its function and operation are the same as IT1.

3. Summary

<1>. The various registers listed above are all for the initialization part of the interrupt program we write. When we initialize part of the program, we can query the meaning of each bit of each register according to specific needs, and assign different values ​​to them according to needs to make them play different functions.

<2>. To write a timer interrupt function, you also need to know how to write an interrupt function, and you also need to write initial values ​​for THn and TLn (n= 0, 1). Then make it clear how the microcontroller works after downloading a specific executable program. These will be recorded in the next note.