Solutions to communication problems between MCU and ARM series processors

　　1 System Hardware Design

　　1.1 Host hardware system structure

　　1) Power supply circuit AT91RM9200 requires 1.8 V and 3.3 V power supplies. In addition, most peripheral devices require 3.3 V power supplies, and a small number of peripheral devices also require 5 V power supplies. Here, the SPX1117M3-3.3 low-dropout (LDO) regulator and SPX1117M3-1.8 low-dropout (LDO) regulator produced by Sipex are selected to provide operating voltage for each device after DC-DC conversion.

　　2) Crystal Oscillator Circuit As shown in Figure 2, the crystal oscillator circuit is used to provide working clocks for AT91RM9200 and other peripheral circuits that require clocks. This system uses passive crystal oscillators X1 (18.432 MHz) and X2 (32.768 kHz) as the system's main oscillator and slow clock oscillator, where the 32.768 kHz crystal oscillator provides the system with a slow clock, and the 18 MHz crystal oscillator provides the system with a 180 MHz master clock through frequency multiplication.

　　3) AT91RM9200 processor ATglRM9200 is a high-performance, low-power 16/32-bit RISC microprocessor based on the ARM920T core of Atmel. Its maximum main frequency is 180 MHz. Its bidirectional, 32-bit external data bus supports 8, 16, and 32-bit data widths, and its 26-bit address bus can address a maximum of 64 MB of space. It is the working and control center of the system.

　　4) Memory The memory module includes two parts: Flash memory and SRAM memory. Flash memory is used to store boot programs, embedded operating systems, user applications and important data. Even if the power is off, the program and data will not be lost. The design uses 28F640J3A produced by Intel, which has a storage capacity of 64 Mb (8 MB), an operating voltage of 2.7 to 3.6 V, a 48-pin TSOP package, and a 16-bit data width.

　　SDRAM memory is the running place of system code, storing programs and data when the system is running, but these programs and data will be lost after power failure. In the design, two SDRAMs with a data width of 16 bits are used in parallel to run as a 32-bit data width SDRAM module.

The SDRAM circuit used is the HY57V651620BTC from Hynix, which has an operating voltage of 3.3 V, a single-chip storage capacity of 4 groups x 16 Mb, a 54-pin TSOP package, is compatible with the LVTTL level interface, and supports automatic refresh and self-refresh.

　　5) The network port uses DAVICOM's DM9161 as the physical layer interface of Ethernet. Through this interface, many physical layer devices can be controlled and configured, status and error information can be obtained, and the working mode and function of the PHY device can be determined. Connect the REF_CLK of DM9161 to the output of 50 MHz crystal oscillator; connect TXD1, TXD2, TXEN, RXD1 and BXD2 of DM9161 to ETXO, ETXI, ETXEN, ERXO and ERXI of AT9lRM9200; connect EXESEN, COL and PWRDWN of DM9161 to high level through 10 kΩ resistors respectively, and connect 6.8 kΩ resistors between BGRESG and BGRES; connect RXEXDV, RXER, RESET, MDC and MDIO of DM9161 to ECRS, ERXER, NRST and EMDIO of AT9lRM9200, and connect light-emitting diodes; connect TX+, TX-, RX+, EMDC, FDX, SPEED and LINKRX of DM9161 to the network isolation transformer.

　　1.2 Slave Hardware Design

　　1) ATmega128 MCU ATMEL's AVR MCU is an enhanced RISC microcontroller with built-in Flash, 128 K bytes of in-system programmable Flash (with read capability during writing, i.e. RWW), 4 K bytes of EEPROM, 4 K bytes of SRAM, 53 general I/O lines, 32 general working registers, real-time clock RTC, 4 flexible timers/counters (T/C) with compare mode and PWM function, 2 USARTs, byte-oriented two-wire interface TWI, 8-channel 10-bit ADC (with optional programmable gain), programmable watchdog timer with on-chip oscillator, SPI serial port, JTAG test interface compatible with IEEEll49.1 specification, and 6 power saving modes that can be selected by software. [page]

　　2) System Control and Reset All I/O registers are set to initial values ​​during reset, and the program starts executing from the reset vector. The instruction at the reset vector must be an absolute jump JMP instruction so that the program jumps to the reset handling routine. If the program never enables interrupts, the interrupt vector can be overwritten by normal program code.

　　3) When the I/O port is used as a general-purpose digital I/O, all AVRI/O ports have true read-modify-write capabilities. The output buffer has symmetrical drive capabilities and can output or absorb large currents to directly drive LEDs.

　　4) SPI serial peripheral interface Serial peripheral interface SPI allows high-speed synchronous data transmission between ATmegal28 and peripherals.

　　5) 16-bit timer/counter The 16-bit T/C can realize accurate program timing, waveform generation and signal measurement. The normal mode, CTC mode, fast PWM mode and phase correction PWM mode of T/C1 and T/C3 are the same as those of T/C0 and T/C2.

　　2 System Software Design

　　The software design of embedded motor control system is divided into host software design and slave software design. The host software design is mainly divided into the host SPI driver and the host communication program.

　　From the perspective of program structure, a device driver is a set of I/O device software interfaces composed of related subroutines and data in the kernel. Its task is to provide interface functions to the system. Therefore, each file system or device has its own interface function, which is a fileoperations data structure, and the components in the structure are almost all function pointers. When the kernel needs to perform special operations on a device, it calls the corresponding interface function, that is, the driver routine. This transfers control from the user process to the driver routine, and when the driver routine completes the control returns to the user process. User-mode programs use standard system calls provided by the kernel to communicate with the kernel. When each system call is used, the kernel switches to the corresponding device driver routine for manipulation.

　　Calling basic interface functions requires the driver's fileoperations structure member to point to open(), read(), write(), release() and other functions. After implementing the various entry point functions in the xxx_fops structure, write the device driver initialization function and register this function when the kernel starts to complete the initialization settings of the hardware device. The initialization program fragment is as follows:

　　void initexxxdevice(viod){

　　/ Check if the hardware device exists, and if so, initialize the internal registers of the hardware device

　　if(result=registerchrdev(254,"xxxdevice",&xxxefops))

　　printk("Error: %dinitxxx_device()can\'tgetMajorln", result);

　　}

　　The function registerchrdev() is called in the device initialization function to complete the character registration. The function form is as follows:

　　intregisterchrdev(unsignedintmajor, constchar*name, structfileoperations*fop);

　　fops is the operation pointer to the implemented fileoperations structure. Based on these parameters, use the following command to create the device file name under /dev.

　　mknod /dev/xxxdevicec2540.

　　3 Conclusion

　　Combining advanced computing technology, semiconductor technology and electronic technology with specific applications in various industries and Internet technology has become the development trend of future embedded systems. This system design is an expansion and application of embedded technology and theory, and an upgrade and improvement of the NETCON network control system. It realizes the real-time monitoring of the status of multiple motors in the motor control system, and can control the speed and phase of any motor. It realizes the communication between the microcontroller and the ARM series processor, and solves the problem of low CPU efficiency in motor control using ARM processor. The solution has been tested and applied with good results, greatly improving the CPU efficiency. However, the speed measurement accuracy of the motor needs to be further improved, the PWM speed regulation range needs to be further increased, and the program needs to be further optimized to improve the real-time performance of the entire system.