Design of multi-channel accurate delay control system based on single chip microcomputer + CPLD

1 Introduction

The control objects in modern control systems may be complex and dispersed, and often work in parallel and independently, but overall they are an organic combination of mutual relevance. Therefore, the timing logic of the control signal requires more precision. CPLD microcontrollers provide technical support for control systems. The multi-machine system composed of CPLD and microcontrollers has the advantages of convenient logic control, precise timing, parallel operation, and friendly human-machine interface. Therefore, this paper proposes a design scheme for a multi-channel precise delay control system based on CPLD and microcontroller control.

2 Design indicators and system principles

2.1 Design indicators

Output multiple positive pulse signals with a pulse width of 10 ms;

Pulse output time is independently adjusted and displayed;

The time adjustment range and accuracy are: the microsecond adjustment range is 1～199μs, and the adjustment accuracy is 1μs; the millisecond adjustment range is 1～199 ms, and the adjustment accuracy is 1 ms;

Provide timing reference signal and working status prompt sound;

9 V battery powered.

2.2 System Design Principles

2.2.1 System Clock

This system design consists of CPLD and multiple single-chip microcomputers. CPLD divides the 24 MHz high-precision integrated crystal oscillator by two to obtain multiple synchronous clock signals as the system clock of multiple single-chip microcomputers, and injects them from the external pulse signal pin XTAL2 of each single-chip microcomputer. The two-way frequency division ensures that the signal duty cycle is 50%, which meets the requirements that the high and low level duration of the single-chip microcomputer clock pulse signal is greater than 20 ns and the maximum pulse frequency is 12 MHz, and also improves the reliability of the system. The 5l series single-chip microcomputer adopts a timing control method with a fixed machine cycle. There are 12 oscillation pulse cycles in one machine cycle, and the machine cycle is 12 divided by the oscillation pulse. This system uses a 12 MHz oscillation pulse frequency, and a fixed machine cycle is 1μs, so it can ensure the highest control accuracy required by the design indicators.

2.2.2 Synchronous timing start signal

This system design uses an external button to provide a start signal. Due to the elasticity of the mechanical contact point and voltage jumps, the button has a jitter effect. To ensure accurate button recognition, this system design uses software de-jittering, and then outputs a stable start signal without voltage glitches through the microcontroller pin. After CPLD conversion, it can provide multiple synchronous timing start signals.

2.2.3 Output Signal

This system design uses a 10 ms single pulse signal as the control output signal of each module unit. The output form can be adjusted through software as needed, and the timing and logical relationship of the system output signal are guaranteed.

2.2.4 System Timing

The system timing diagram is shown in Figure 1. Driven by the timing pulse, the key signal is transformed through de-jittering and CPLD logic synchronization to form a timing start signal (0-n). The leading edge of the timing reference pulse is used as the timing starting point. After the delay is set, the system outputs the corresponding output signal. The delay time can be adjusted independently, and the signal output form can be set by software programming. Figure 1 uses a single positive pulse as the output signal. [page]

2.2.5 System Principle Block Diagram

The power supply voltage regulator unit realizes the voltage regulation and filtering of the system 5 V power supply. The single-chip microcomputer adopts the external system clock. The main control single-chip microcomputer CPUO completes the functions of key detection, timing reference signal output and system prompt sound output. The NO.1~N0.n units complete the functions of time adjustment and display, μs/ms (microseconds/milliseconds) conversion and signal output, and the CPLD completes the clock 2-frequency division, synchronous timing pulse output and timing start signal synchronous output. Figure 2 is a principle block diagram of a multi-channel precision delay control system. [page]

3 Hardware Circuit Design

3.1 Main control unit

Each system is composed of an independent main control unit, as shown in Figure 3. The main control unit consists of voltage, CPUO and CPLD synchronous control modules. The voltage module completes the conversion and filtering from the rechargeable battery voltage to the stable 5 V system power supply. The CPUO unit module uses the AT89S52A, a 51 series single-chip microcomputer of ATMEL. AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8 KB in-system programmable Flash memory, 256 bytes of random access data memory (RAM), 32 external bidirectional input/output (I/O) ports, 5 interrupt priority levels, 2-level interrupt nesting interrupts, 2 16-bit programmable timer counters, 2 full-duplex serial communication ports, watchdog (WDT) circuit, on-chip clock oscillator, and compatible with the standard MCS-51 instruction system. The CPUO module completes the functions of key signal detection, working status prompt sound output, timing reference signal output, etc. The CPLD synchronous control module uses the EPM7032SLC44 of ALTRA as the control core. EPM7032SLC44 is a MAX7000 CPLD, which is based on the advanced multi-array matrix (MAX) architecture and uses advanced CMOS manufacturing technology. It provides a density range from 32 to 512 macro cells and a pin-to-pin delay of 3.5 ns. It supports in-system programmability (ISP) and can be reconfigured on site. The CPLD synchronization control unit completes clock division and synchronization, key signal synchronization and other functions. The ProKram socket is the programming interface of the CPLD. [page]

3.2 Output Control Unit

Each system consists of n (n=9 in this system design) output control units, and these n unit output controls work independently and in parallel, as shown in Figure 4. N0.1~N0.n are based on the 5l series single-chip microcomputer AT89C2051 of ATMEL Company. AT89C2051 is a low-power, high-performance CMOS 8-bit single-chip microcomputer with 15 bidirectional input/output (I/O) ports, 2 K bytes of repeatedly erasable read-only Flash program memory and 128 bytes of random access data memory (RAM); it is produced using ATMEL's high-density, non-volatile storage technology and is compatible with the standard MCS-5l instruction system. The output control units (NO.1~NO.n) work in parallel to complete the functions of delay time setting, μs/ms conversion setting, control signal output and delay display. The delay time display is realized through the serial port of the single-chip microcomputer, and three common anode digital tubes are driven by three serial/parallel conversion devices 74LS164.

4 System Software Design

The system software design includes CPUO unit, NO.1~NO.n output unit and CPLD unit programming. Due to the strict time requirements, it is written in assembly language, and the signal output is completed by the interrupt program. Since the interrupt response process, scene protection and the necessary setting condition detection after the interruption take time, the software must use the delay of the redundant instruction (such as NOP) to ensure that the counter0 output and the control signal delay start point are at the same time. [page]

The program flow of CPU0 unit is shown in Figure 5. The main program of CPU0 completes system initialization, key detection, de-jitter signal output and working status prompt sound output, and the interrupt service program outputs the timing reference signal counterO. The program flow of output control unit NO.1-NO.n is shown in Figure 6. The main program of each unit completes μs/ms setting detection, delay setting reading, delay time display, and the interrupt program completes the control signal output function. The CPLD program is written in VHDL language and compiled and simulated using QHalftusⅡ software.

5 Conclusion

The system design can be applied to the discharge control system of capacitor groups (9 capacitors). In the discharge electronic switch control end, load end measurement and microsecond delay range, the delay error is less than 0.1μs, and in the millisecond delay range, the delay error is less than 50μs. Actual tests show that the system achieves the adjustment accuracy required by the design. The multi-channel precise delay control system based on single-chip microcomputer + CPLD makes full use of the respective characteristics of single-chip microcomputer and CPLD to achieve the main design indicators. Practical application proves that the system can fully meet the control requirements of strict control systems in sequential logic requirements.