Application of Ordinary Switches in IEEE 1588 Clock Synchronization System

introduction

With the rapid development of information technology and microelectronics technology, more and more distributed measurement and control systems based on network environments have emerged in the fields of power systems, manufacturing, process control, etc., and clock synchronization technology has become a necessary means to ensure the performance of distributed systems. The IEEE 1588 Precision Time Protocol (PTP) will be widely used in the field of distributed control due to its high precision (sub-microsecond clock synchronization can be achieved), high reliability, and Ethernet (UDP/IP)-based synchronization method. However, under the current conditions, the IEEE 1588 protocol is far from realizing its application potential. Because the clock synchronization network defined by the protocol requires the use of a very expensive transparent clock switch as a network connection device. Therefore, IEEE 1588 currently mainly plays a role in important facilities such as digital substations. For most distributed measurement and control systems, if transparent clock switches are used, the system cost will inevitably increase significantly, thus greatly limiting the application of the protocol.

In fact, different distributed systems have very different requirements for clock accuracy. Only a few hard real-time systems with high requirements for measurement accuracy and control performance require microsecond-level clock synchronization accuracy. Taking the power system as an example, the IEC 61850 standard defines five levels of clock synchronization accuracy (T1~T5), and only the highest T5 requires a synchronization accuracy of 1μs. The existing microprocessors and physical layer chips that support IEEE 1588 can ensure that the point-to-point synchronization accuracy of two embedded intelligent electrical devices (IEDs) reaches the microsecond level. Even if affected by network transmission delays, it is still possible to achieve synchronization accuracy of T1~T4 levels. In future distributed measurement and control systems, there will be more and more sensors, actuators and control units with embedded microcontrollers as the core. Therefore, a cost-effective technical solution that can meet the clock synchronization requirements of different applications in distributed systems will have a very wide range of application value.

To this end, this paper explores the application of ordinary switches in IEEE 1588 clock synchronization networks in distributed systems with a large number of embedded devices. Through a large amount of experimental data, the impact of synchronization message delay caused by the use of ordinary switches in IEEE 1588 systems on clock synchronization accuracy is analyzed, as well as the clock synchronization effect that can be achieved by IEEE 1588 systems using switches with different performance. The work in this paper can provide a reference for the further promotion and popularization of the IEEE 1588 protocol in distributed measurement and control systems.

1 IEEE 1588 clock synchronization mechanism

The clock synchronization mechanism of the IEEE 1588 protocol stipulates that the system works in master-slave mode, with the master clock (Master) providing the clock reference to the slave clock. The specific implementation method is: the master clock periodically sends a synchronization message (Sync), and the slave clock calculates the time delay of the message transmission and the deviation between the master and slave clocks based on the time when the Sync message is received, and adjusts the local time to keep it consistent with the master clock.

The master-slave clock offset measurement of the IEEE 1588 system is shown in Figure 1. The master-slave clock offset is calculated as follows:

offsetFromMaster=[(TS1-TM1)-(TM2-TS2)]/2

2 Clock Synchronization Test System

The hardware structure of the IED controller supporting the IEEE 1588 protocol used in this paper is shown in Figure 2. The main control chip is the STM32F107VC of the ARM C0rtex-M3 series equipped with an Ethernet MAC layer interface module (MII), and the peripheral modules connected to it include USB interface, serial port EEPROM and real-time clock, etc. The PHY layer Ethernet chip is DP83640, which is equipped with a high-precision IEEE 1588 clock and a hardware time stamp function. It can timestamp the received/sent messages at the physical layer, thereby eliminating the delay and jitter generated by the MAC layer and the IEEE 1588 protocol stack, thereby effectively ensuring the accuracy of clock synchronization.

The composition and experimental device of the clock synchronization test system are shown in Figure 3 and Figure 4 respectively. The master clock node receives the reference time information from the GPS timing module through the serial port, and then sends the clock synchronization message of the IEEE 1588 protocol to the slave node through the ordinary switch. The clock synchronization accuracy of the system is tested by the time difference of the second pulse generated by the master and slave nodes.

3 Experimental results and analysis

The clock synchronization test experiment in this article is divided into two parts: ① The master clock node is connected to the two slave nodes through a 1000M Ethernet switch; ② The master and slave clocks are connected through 100M and 1000M switches respectively. [page]

In the IEEE 1588 system, the shorter the synchronization message sending period, the higher the clock synchronization accuracy. However, as the synchronization message sending period decreases, the network traffic in the system increases. In practical applications, the network burden will also increase, which may reduce the system clock synchronization performance during operation. Therefore, the experiments in this paper choose the master node synchronization message sending period of 2 s.

3.1 Clock synchronization test data

Figure 5 is the clock synchronization error curve of the two slave nodes in Experiment 1 (a total of 500 clock synchronizations), and Table 1 is the relevant experimental data statistics. The experimental data show that under the same test conditions, both slave nodes can achieve sub-microsecond synchronization accuracy (the average deviation of the second pulse is about 270 ns, and the maximum deviation is 450 ns).

The clock synchronization error curve of Experiment 2 is shown in Figure 6, and the relevant experimental data statistics are listed in Table 2. The experimental data show that when two slave nodes are connected to the master node through the same switch and there is no other network traffic, the average clock synchronization error between the master and slave nodes using a 100M Ethernet switch is about 300 nanoseconds, and the maximum error is 500 ns, which is slightly lower than the synchronization accuracy of a 1000M switch (average error 273 ns, maximum error 450 ns).

3.2 Test Results Analysis

In order to further analyze the results of the clock synchronization test, this paper lists the following data for comparison: ① Typical data statistics of the two groups of experimental test results, as listed in Table 1 and Table 2 respectively; ② The synchronization error bar chart obtained by using 100M and 1000M switches in Experiment 2, as shown in Figure 7.

As can be seen from Table 1 and Figure 5, under the same test conditions (i.e., the two slave nodes are connected to the master node by the same switch and there is no other network traffic), the clock synchronization effects of the two slave nodes are basically the same, and the synchronization error can reach the sub-microsecond level. Comparing the clock synchronization error curve in Figure 6 and the synchronization error bar chart in Figure 7, it can be seen that in the absence of other network traffic, both the 100M switch and the 1000M switch can achieve sub-microsecond clock synchronization accuracy, and the 1000M switch is slightly better than the 100M switch in terms of synchronization accuracy.

The clock synchronization test results conducted in this paper are based on the following network conditions: ① The master and slave clock nodes are connected through a simple network structure; ② There is no other network traffic in the system. The above conditions seem to be close to the ideal state, but they are still very close to the actual measurement and control system network environment. The reasons are: ① The IED nodes such as sensors, controllers and actuators in the distributed measurement and control system are usually connected through a network with a simple topology structure, that is, the nodes are connected to each other through a single-stage network connection device (such as a switch); ② The information transmitted in the communication network of the distributed system is mainly various measurement data and control instructions, with very little data content, so the network traffic is also very small. Therefore, the network delay jitter in these data transmission processes is very small, and no congestion will occur when passing through the switch, and the transmission delay asymmetry problem caused by the different data traffic between different ports inside the switch can also be ignored.

In summary, for distributed measurement and control systems with relatively simple communication network topology (such as single-stage switches connecting nodes) and small network traffic (usually only transmitting a small amount of measurement information, control instructions and other data), using ordinary Ethernet switches can also achieve high clock synchronization accuracy. The research results of this paper can provide a reference for the further promotion and popularization of the IEEE 1588 protocol in distributed measurement and control systems.

Conclusion

This paper discusses the application of IEEE 1588 clock synchronization using ordinary Ethernet switches in distributed measurement and control systems with relatively simple communication network structures. Through a large amount of experimental data, the influence of synchronization message delay caused by the use of ordinary switches in IEEE 1588 systems on clock synchronization accuracy is analyzed, as well as the clock synchronization effect that can be achieved by IEEE 1588 systems using switches with different performance. The research results show that when the master and slave clock nodes are directly connected through switches and the network traffic is very small, microsecond-level clock synchronization accuracy can still be achieved, thereby verifying the feasibility of ordinary switches. Therefore, the research work in this paper can provide a reference for the further promotion and popularization of the IEEE1588 protocol in distributed measurement and control systems.