Multi-channel data acquisition based on CS5321 and CS5322

     introduction

　  There are three advantages to using ∑-△A/D: first, the front end of the ∑-△A/D converter does not need to be equipped with a steep anti-aliasing analog filter or a sampling and holding circuit; second, since the ∑-△A/D can directly perform high-precision conversion on analog signals with a large dynamic range, there is no need to add a programmable amplifier; finally, since the ∑-△A/D generally uses serial data transmission, if the system is designed properly, the interface circuit will be very simple.

　　CS5321 and CS5322 are ∑-△ modulator and programmable multi-stage FIR linear phase digital decimation filter respectively. The combination of the two can obtain a 24-bit high-precision A/D converter system. Their interface circuit is shown in Figure 1. The operating frequency band of CS5321 is 0~1500 Hz, and it can output two oversampled 1-bit ∑-△ bit streams at different rates. CS5322 is a special digital decimation filter designed for CS5321. It is a 3-stage decimation digital filter with variable sampling rate. By programming its three control bits DECC, DECB, and DECA, seven different output decimation rates of 4 kHz, 2 kHz, 1 kHz, 500 Hz, 250 Hz, 125 Hz, and 62.5 Hz can be obtained. The output word length is 24 bits, and it is output from the SOD pin of CS5322 in the form of a bit stream in the serial port read mode.

　　Based on these characteristics of CS5321 and CS5322, when selecting the system's central processing and control unit, it is best to choose a DSP or other microprocessor with a 32-bit word length and a serial port. 

　1 Overall interface of the system

　Based on the above introduction and the consideration that the entire system adopts serial transmission, the overall interface block diagram of the acquisition system is shown in Figure 2. 

　 As shown in Figure 1, the multi-channel analog signal is first sent to the respective ∑-△ A/D converter through the preamplifier, and the obtained multi-channel digital signal is transmitted to the central processing control unit through the serial port under the action of the multi-channel control circuit, and can be sent to the memory for storage after appropriate processing. The key to the design of the entire system lies in the multi-channel serial port interface design, which is introduced below.

　 2 Design Principle and Implementation of Multi-channel Serial Interface

　　As we can see from the previous introduction, the CS5322 outputs a 24-bit serial bit stream. It only needs to add a small amount of multi-channel control logic to realize the direct connection between the multi-channel A/D converter and the DSP, and there is almost no need to add any other interface logic circuits. The following starts with analyzing the working sequence of the ∑-△ A/D converter and introduces the principle and specific implementation of the acquisition system in detail.

　　2.1 ∑-△ A/D converter serial port read operation timing

　　The serial port read operation timing of the ∑-△ A/D converter composed of CS5321/CS5322 is shown in Figure 3. 

　  When the input clock (CLKIN) of CS5321/CS5322 is 1 MHz, the modulator (CS5321) outputs a serial sampling bit stream with a rate of 256 Kb/s. By assigning different values ​​to the decimation rate control bits (DECC, DECB, DECA) of CS5322, 7 different output word rates (i.e. sampling frequencies) can be generated, with a word length of 24 bits. The initialization of CS5322 can be done through software programming or by directly setting the bits in hardware. The specific method to be used can be selected according to the needs of the system. [page]

　  The DRDY of CS5322 is the data ready signal pin. When DRDY is high, it means that the ∑-△ A/D converter composed of CS5321/CS5322 has completed a conversion, and the data has been prepared in its output buffer by CS5322, and the data can be output from the serial port. The read operation control pins in CS5322 are CS, R/W, SCLK, and SOD. When CS=0 and R/W=1, the serial port is in a valid read operation. The RSEL pin is used to select whether the serial port outputs the data buffer or the data of the status buffer. SOD is the serial data output pin. When the read state is selected, regardless of whether SCLK is high or low, the first bit of output data will appear on the SOD pin and terminate at the falling edge of SCLK. After the first SCLK falling edge, each SCLK rising edge outputs one bit of data from the SOD pin. The output bit stream order is high bit (MSB) first and low bit (LSB) last.

　   2.2 Principle of Multi-channel Serial Interface

　  Through the above analysis of the serial read operation timing of CS5322, we can get the traditional solution of multi-channel data acquisition system implemented by CS5321/CS5322. Taking M channel as an example, the block diagram of the system is shown in Figure 4.

　 In the multi-channel acquisition system of the ∑-△ A/D converter composed of CS5321/CS5322, the traditional solution is shown in Figure 4. The controller turns on the DRDY signal of each channel, and when DRDY is high, each channel outputs data to the controller from the SOD pin in turn. The sampling rate of the ∑-△ A/D converter composed of CS5321/CS5322 is set by the three bits DECC, DECB, and DECA, and can be 7 types such as 62.5 Hz to 4 kHz. For each sampling rate, the minimum frequency of the shift clock (SCLK) required is fmin=fs×24 (fs is the sampling rate). In typical usage, it is only necessary to design a clock source according to the sampling rate requirements so that its frequency is slightly higher than fmin. The timing diagram is shown in Figure 5.

      2.3 Improvements to Traditional Solutions

　   According to the above scheme, although the design of the multi-channel data acquisition system can be completed, the cycle (T=m×24/fs) of the multi-channel data acquisition system designed with this scheme to complete a multi-channel data acquisition transmission is very long, especially as m increases, that is, the number of channels increases.

　  Through further research on CS5321/CS5322, it is found that the minimum period required by CS5322 for SCLK can be 100 ns, which is much higher than the shift clock frequency used in traditional design methods. Therefore, the data read rate can be increased by speeding up the serial shift clock (SCLK), thereby realizing the reading of multiple channels of data within one sampling cycle.

      Assuming that the frequency of SCLK is fb, the shift time required for each channel of 24-bit data is tm=24/fb, and the sampling period is Ts=1/fs (fs can be 62.5 Hz, 125 Hz, 250 Hz, 500 Hz, 1 kHz, 2 kHz, 4 kHz), the maximum value of fb can reach 10 MHz, as long as fb is properly increased, tm < Ts, so that at most Ts/tm channels of data can be transmitted in one sampling period, greatly improving the speed of multi-channel data acquisition and transmission. For example, when fs=1 kHz, fb=1 MHz, it can be seen from the above analysis that in theory, at most 42 channels of serial data can be transmitted in one sampling period. Considering various factors such as device delay, the actual application should be smaller than this theoretical value.

　  The improved wiring diagram is based on Figure 4, but without the dotted part, and directly connects the DRDY of the first channel to the FSR. Improved scheme Figure 6 Schematic diagram of multi-channel data acquisition timing of the improved scheme The improved multi-channel ∑-△ A/D converter performs convolution operation and data conversion at the same time, and generates DRDY signals almost at the same time, but only the DRDY signal of the first channel is connected to the frame synchronization pin (FSR) of the controller to trigger the serial port of the processor to receive 1 frame of data. The chip select CS1, CS2...CSm of each channel is selected in sequence by the controller in a sampling cycle, and the SOD pin of each channel is directly connected to the DR pin of the controller. The shift clock of the entire system can be provided by an external clock source or generated by the controller.

　  The data acquisition process of the entire system is as follows: ① Initialization, start A/D. ② Set the R/W of the A/D converter to a high level and set the sampling rate. ③ When DRDY becomes a high level, CS1 is enabled and the first channel of data acquisition begins; when all 24 bits of data are received and the first channel is completed, CS2 is enabled and the second channel of acquisition begins, and M channels of data acquisition are completed in sequence. ④ Store and process the data.

       Conclusion

　 At present, the multi-channel data acquisition system based on CS5321 and CS5322 has been applied in the fields of oil exploration and seismic data acquisition. Compared with other data acquisition systems with corresponding purposes, this system has faster acquisition rate, higher accuracy and better real-time performance. The design idea of ​​the multi-channel data acquisition system introduced in this article has certain universality, and some improvements have been made to the traditional scheme, which can further improve the acquisition rate of the entire system.