Design and implementation of touch screen controller IP core based on SOPC

    System on Programmable Chip (SOPC) is a special embedded system with flexible design and in-system programmable functions of software and hardware. SOPC is based on integrated circuit IP core in design. The self-developed SOPC IP core customizes the display control function according to the actual hardware resources and functional task requirements, which can enhance system reliability and design flexibility and reduce costs. At present, there are many articles on controller IP core designed for LCD display screens, but there are fewer articles on controller IP core designed for TFT-LCD touch screens, and these articles rarely include simulation verification of each module of the controller.
    This paper proposes a design method for TFT-LCD touch screen controller IP core. The controller has an Avalon bus interface and together with other standard IP cores constitutes a system on chip with NiosⅡ as the core. In view of the characteristics of the touch screen frame buffer read operation in this design, the module is developed in the form of Avalon master port interface, which greatly improves the processor operation efficiency. At the same time, the parameterized design of the touch screen controller IP core is realized, which improves the reusability of the controller for different LCD screens. Finally, the problem of data readout clock and pixel clock being out of sync is solved by using the output buffer FIFO.

1 Overall structure of touch screen controller
    A storage space is opened in SDRAM to store screen image data, which is called frame buffer. By designing appropriate hardware logic to establish a one-to-one correspondence between frame buffer and screen image pixels, and coordinating the row and field timing signals required for touch screen display, the data in the frame buffer is continuously transmitted to the touch screen to complete the final display refresh. Its overall structure is shown in Figure 1.

    At the beginning of the touch screen controller refresh cycle, the master port module completes the master port read operation according to the address generated by the frame buffer address generation logic, realizes the data reading in the frame buffer, and transmits the data to the output buffer module. At the same time, the timing signal generation module generates line and field synchronization signals according to the timing specification of the touch screen, as well as the horizontal and vertical coordinates of the relevant display points synchronized with the pixels. The touch screen controller data display module continuously reads the screen display data from the cache.

2 Touch screen controller module design
2.1 Avalon-MM Slave interface module
    This module is mounted on the Avalon bus as a slave device to configure and control all user logic. The core function is register operation, including reading, writing, and the generation and conversion of some special indications and status signals. The data obtained from the slave port is assigned to the corresponding registers respectively. The registers are divided into: FIFO address register, coordinate register, and one frame data length odd register. This module is the interface circuit that finally realizes the graphic display function on the touch screen.
2.2 Avalon-MM Master interface module
    The function of the LCD controller is to generate LCD timing signals and output the image information in the frame buffer in an orderly manner. Since the graphics are output to the touch screen frame by frame, and the display refresh process is an infinite loop, the frame buffer read operation must be performed repeatedly. Therefore, this design performs hardware acceleration on the above read operation. Image data can be continuously read from the FIFO, and image data is read during the effective time period of line, field and touch screen display. Image data is not read at other times. This reduces the use of the Avalon bus, is conducive to image display and reduces the bus burden. Analysis of the frame buffer read operation shows that the process always reads the data in the memory for display output in a certain order, and the regularity is very strong.
    This module mainly completes the generation of address and operation timing, pixel data cache write operation control, data width conversion and other functions.
2.3 Touch screen timing generation module The
    touch screen in this article has 5 lead-out signal lines: pixel data signal, touch screen clock signal, line synchronization signal, field synchronization signal, and enable signal. In order to achieve normal display of the touch screen, the above signals must be driven according to the standard timing. Among them, the line and field synchronization signals are used to mark the display time of a line and a frame of the image on the screen respectively. The screen scan lines are scanned from top to bottom and from left to right. In this process, the image pixel data in the frame buffer can be output in sequence to realize the screen image display.
2.4 FIFO frame buffer module The
    DDR controller continuously writes data to the FIFO with the system clock. When a frame of data is full, it will no longer be in the write state, but wait for the LCD controller to read the state. The color processor obtains data from the FIFO, reads 32 bits of data from the FIFO each time and continuously sends it to the LCD.
    The color processor regards each byte as a pixel data and converts one byte of pixel data into 3 bytes of RGB data. The color processor reads data from the synchronous FIFO buffer. When the synchronous FIFO buffer writes and reads without conflict, the synchronous FIFO buffer generates a read request, allowing the Avalon master port to initiate a read transmission to the Avalon bus. The data obtained from the bus will be written into the synchronous FIFO buffer. The color processor reads the pixel value from the FIFO and transmits it to the LCD display module.
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3 Modelsim simulation and test
    1) Avalon slave port simulation and test
    As shown in Figure 2, one bit address of the slave port corresponds to one bit of data. When the write signal is valid, the data is written to the corresponding register; when the read signal is valid, the corresponding register address outputs the data. The LCD module is controlled by writing data from the slave port, and the LCD reads the first address of the image and the length of the read data.

    2) Avalon master port simulation and test
    The function of the Avalon module is to respond to the read request of the Avalon master port and output the corresponding data in the FIFO to the Avalon master port. Through the read signal and the corresponding address master port, the image data is continuously read from the FIFO and transmitted to the LCD according to the LCD timing. Figure 3 is a simulation waveform diagram when the Avalon master port reads data from the video memory.

    3) LCD image display module test
    The LCD display module displays the image data read from the FIFO on the touch screen. As can be seen from Figure 4, when DEN is valid, the pixel data is divided into R, G, and B and sent to the LCD. HCount and VCount are the row counter and field counter, and each pixel is sent to the touch screen with the LCD clock.

4 Hardware design of touch screen system based on SOPC The
    hardware design of touch screen system based on SOPC is shown in Figure 5, where the SDRAM controller realizes data access between the processor and SDRAM, including SDRAM storage of programs and data such as characters, graphics, and colors: JTAG UART realizes communication between PC and development board, which is mainly used for debugging, inputs corresponding data from the keyboard, and then debugs the processor through NiosⅡ software, and transmits the data to the touch screen through the LCD interface for display.

    The development board uses the H3C40-V6 development board of Dalian Yuhua Company. The FPGA chip on the board is EP3C40F484C6, and the touch screen is a 4.3-inch color digital TFT-LCD touch screen with a resolution of 800×484, which can display text, color pictures, etc. The board comes with a touch screen display driver.

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    According to the peripherals and device characteristics used, the peripheral modules to be added to the system are established in SOPC Builder, mainly including: NiosⅡ, SDRAM controller, JTAG UART, clock bridge, tri-state bridge, phase-locked loop and PIO, etc. After setting various parameters, add LCD controller and connect the Avalon master port interface of LCD controller to SDRAM. The
    QuartusⅡ top-level module containing NiosⅡ system is created, as shown in Figure 6.

5. SOPC-based touch screen system software design
    Write a software test program based on the hardware design to verify the LCD touch screen display. First, write the predetermined data into the video memory to initialize the video memory, then write the corresponding parameters into each control register of the LCD through programming, and finally enable the LCD controller to observe whether the display output of the display is correct.

    This design uses C language programming to display color bars on the touch screen. On the NiosⅡIDE software platform, create a C/C++ project, configure the system properties of the project, and then compile and run the program. After successful compilation, it is automatically downloaded to the hardware platform to start running the program. At this time, the effect observed on the touch screen is shown in Figure 7. The colors of the color bars from top to bottom are red, light green, blue, green, pink, red, purple, white, and blue.

6 Conclusion
    Customized touch screen interface control module is used to customize user logic peripherals. Use hardware description language to establish the controller module and perform simulation tests; use parameterized component design to make it have strong versatility and compatibility. The controller IP core design effectively utilizes FPGA resources, saves costs, enhances system reliability and design flexibility, and has strong portability.