Realizing the Railway Data Real-time Acquisition System Using S3C2410

　　2.4 Sensor Module

　　The sensor module can be selected according to the data to be collected. This system is mainly used for measuring the vibration of train locomotive bodies, so three acceleration measurement modules made of ADXL105 high-precision single-axis acceleration sensor chips are used. The measurement modules are placed in the vertical and horizontal directions at the bottom of the body to measure the acceleration of the body in the X, Y, and Z directions. The measurement data is input into the precision amplifier in the form of a differential signal, and is directly sent to the A/D module after comparison and amplification.

　　2.5 External communication module

　　The external communication module consists of two parts: 485 communication module and CDMA module.

　　The 485 communication interface uses the MAX1490 chip from MAXIM. This is a completely isolated 485 data interface chip that works in simplex mode and has a maximum transmission baud rate of 2.5 Mbps. Its output pin is directly connected to the serial port 2 (UART2) of the ARM processor; the ARM processor reads the broadcast information of relevant data such as time and coordinates through serial port 2. The serial port 0 (UART0) of the ARM processor is connected to the AnyData DTGS800 CDMA module; the monitoring data is sent to the ground server through the CDMA module after preprocessing.

　　3 Software Design

　　Software design mainly uses Embedded Visual C++ and VHDL. VHDL is used to write FPGA programs, while C is used to debug ARM processors.

　　After the system starts working, the FIFO in the ARM processor and FPGA coprocessor begins to initialize. The data after A/D conversion is stored in the FIFO corresponding to the three data output channels. When the data capacity in the FIFO reaches a certain limit, an interrupt is generated, and the main program in the ARM processor generates an interrupt waiting thread; once an interrupt is generated, the interrupt service program is entered to read the data. The data is pre-processed by the detection program and sent out through the CDMA module. Figure 3 is a system workflow diagram.

Figure 3 System workflow diagram

　　3.1 System Synchronization

　　Because the A/D module and FPGA coprocessor start working as soon as they are powered on and the ARM processor completes system loading, it takes about 10 seconds for the port to be initialized. During this process, the data stored in the FIFO has been filled. If the ARM processor directly uses this part of the data after the program is loaded, the problem of mismatch between the detection result and the broadcast information will occur. In order to prevent the system from having data detection errors due to the confusion of the working timing of each module. After the ARM completes the Windows CE system loading and enters the main detection program, a clear signal is generated to clear the data in the three FIFOs. The system works synchronously.

　　3.2 Interrupt Generation and Processing

　　In this system, if the A/D conversion data is read in real time, the ARM processor will inevitably have a low working efficiency, so the interrupt method is used in the circuit design. The output data of the A/D module is written into three FIFOs in a cyclic manner. Once the available data capacity in the FIFO is reduced to a certain limit, an interrupt is generated, and the ARM processor enters the interrupt service routine and reads the data in the FIFO.

　　3.3 Reading train broadcast information

　　The train locomotive broadcast information is continuously sent through the monitoring equipment. Information transmission is carried out using the standard RS485 transmission protocol, and the communication baud rate is 9600

bps, using 10-bit asynchronous communication mode: 1 start bit + 8 data bits + 1 stop bit. Each data packet consists of 17 bytes of data, including month, day, hour, minute, second, speed, kilometer mark, route number and train number. The data format is: start bit + data bit + stop bit + BCC check. Among them: the start bit is 1 byte, fixed to 0x02; the data bit is 14 bytes; the stop bit is 1 byte, fixed to 0x03; the BBC check is 1 byte, which is the "exclusive OR" check of the previous 15 bytes.

　　Software implementation: The implementation of the program for receiving broadcast information mainly utilizes the Windows message mechanism. First, initialize the UART2 port of the S3C2410 chip, including setting the baud rate to 9600 bps, configuring the port, and binding the port to the event. Then start the thread to continuously listen to the port. If there is data input, a read event will be generated. At this time, the thread reads a byte of data and sends the data to the main thread through the serial port. Finally, the main thread receives data through the corresponding function, and performs length detection and XOR verification on the data after the data is received. If the test passes, the data is transferred to the secondary cache (the primary cache continues to store data), and the upper module is notified to read the data; then the secondary cache is cleared and waits for the next data to enter. The interface of the broadcast information reading program is shown in Figure 4.

　　3.4 Acceleration data acquisition

　　Data collection is accomplished through the interaction between the application and the driver. There are many ways to achieve interaction, such as using a callback function or passing the data processing function pointer in the function application to the driver, and using SETEVENT. Considering the software upgrade, this system uses the SETEVENT method. There is a big difference between the Windows CE system and the system on the PC. Once some modules of the system are changed, the Windows CE system must be recompiled and the FLASH must be burned, which is a lot of work. The SETEVENT method can be used to debug the application without changing the driver, thus avoiding repeated burning of the FLASH.

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　　Software design idea: After the data acquisition software is started, the data in the FIFO must be reset. Because it takes 15 seconds from the start of the Windows CE system to the start of the data acquisition software, but the A/D module and FIFO module start working after the system is powered on, so if this part of the data is used, it will cause the data to not match the train broadcast information. After responding to the interrupt, the driver notifies the application through the SETEVENT mechanism. At this time, the control of data reading is completely handed over to the top-level user. The user can control the reading and processing of data according to his own needs. The interface of the data acquisition program is shown in Figure 5.

　　4 Conclusion

　　The system developed in this paper makes comprehensive use of technologies such as mobile communication and embedded system design. Compared with traditional detection equipment, it greatly improves the real-time and systematic nature of line monitoring. At the same time, the system focuses on the research of monitoring data processing and detection methods, and applies them in practical systems.

　　The flexibility and versatility of the circuit are fully considered in the design of this system. The corresponding VHDL language program can be written according to different functional requirements. The Windows CE operating system used by the system can be arbitrarily tailored, which is very helpful for the conversion of functions. The system has been developed and is now in the field experiment stage.