Watchdog Working Principle and Timer Operation

　　The S3C44B0X watchdog timer is used to continue the control operation in the case of interference such as noise and system errors. It can also be used as a 16-bit internal timer to request interrupt service. The watchdog timer generates a reset signal every 128 MCLK cycles. When the program is executed normally, the watchdog timer needs to be continuously cleared to 0, that is, the "feed the dog" operation, to prevent the occurrence of a reset signal. In this way, when the system program is "runaway" due to external interference, the entire system is reset because it cannot be "fed" in time, so that the system program restarts, ensuring the safety and reliability of the system.

　　2. Watchdog timer operation

　　As shown in the figure is the functional block diagram of the watchdog timer.

　　Figure 1. Functional block diagram of the watchdog timer

　　The S3C44B0X watchdog timer uses MCLK as the clock source, and obtains the required frequency after 8-bit pre-scaling and 4-to-1 2-bit division. The pre-scaling value and frequency division value are configured in the watchdog timer control register WTCON. The effective pre-scaling value range is 0 to 28-1, and the frequency division coefficient can be selected as 16, 32, 64 or 128. Use the following formula to calculate the watchdog timer frequency and each timer clock period value.

　　twatchdog=1/MCLK/(pre-division value+1)/division coefficient

　　After the watchdog timer is enabled, WTDAT (watchdog timer data register) cannot be automatically loaded into WTCNT (watchdog timer count register). Therefore, before the watchdog timer starts working, the initial value must be written into the watchdog timer count register WTCNT.