NandFlash Series 2: Analysis of S3C2410 Reading and Writing Nand Flash

　　1. Structural analysis

　　The S3C2410 processor integrates an 8-bit NandFlash controller. Currently, the common 8-bit NandFlash on the market include Samsung's k9f1208, k9f1g08, k9f2g08, etc. The data page sizes of k9f1208, k9f1g08, and k9f2g08 are 512Byte, 2kByte, and 2kByte respectively. They have certain differences in addressing methods, so the program codes are not universal. This article takes the S3C2410 processor and k9f1208 system as examples to describe the reading and writing methods of NandFlash.

　　NandFlash data is stored in memory cells in bit form. Generally speaking, a cell can only store one bit. These cells are connected into bit lines in units of 8 or 16, forming the so-called byte (x8)/word (x16), which is the bit width of NAND Device. These lines form pages, and pages are organized into a block. The relevant data of k9f1208 is as follows:

　　1block=32page；1page=528byte=512byte(Main Area)+16byte(Spare Area)。

　　Total capacity = 4096 (number of blocks) * 32 (page/block) * 512 (byte/page) = 64Mbyte

　　NandFlash reads and writes data in pages and erases data in blocks. According to the organization of k9f1208, there are four types of addresses: Column Address, halfpage pointer, Page Address, Block Address. A[0:25] indicates the address of the data in the 64M space.

　　Column Address indicates the address of the data in the half page, ranging from 0 to 255, represented by A[0:7];

　　The halfpage pointer indicates the position of the half page in the whole page, that is, in the 0~255 space or in the 256~511 space, represented by A[8];

　　Page Address indicates the address of the page in the block, ranging from 0 to 31, represented by A[13:9];

　　Block Address indicates the location of the block in the flash, with a size range of 0 to 4095, represented by A[25:14];

　　2. Read Operation Process

　　The addressing of K9f1208 is divided into 4 cycles: A[0:7], A[9:16], A[17:24], and A[25].

　　The process of the read operation is: 1. Send the read command; 2. Send the first cycle address; 3. Send the second cycle address; 4. Send the third cycle address; 5. Send the fourth cycle address; 6. Read data to the end of the page.

　　K9f1208 provides two read instructions, '0x00' and '0x01'. The difference between these two instructions is that '0x00' can set A[8] to 0, selecting the upper half of the page, while '0x01' can set A[8] to 1, selecting the lower half of the page.

　　Although the reading and writing process does not need to start from the page boundary, it is recommended to start reading and writing from the page boundary to the end of the page in formal occasions. The following explains the reading process by analyzing the code for reading the page.

　　static void ReadPage(U32 addr, U8 *buf) //addr indicates the page number in the flash, i.e. 'flash address >> 9'

　　{

　　U16 and;

　　NFChipEn(); //Enable NandFlash

　　WrNFCMD(READCMD0); //Send the read command '0x00'. Since it is a full page read, the command '0x00' is selected.

　　WrNFAddr(0); //The first cycle of the write address, that is, Column Address, is 0 because it is a full page read.

　　WrNFAddr(addr); //The second cycle of the write address, i.e. A[9:16]

　　WrNFAddr(addr>>8); //The third cycle of the write address, i.e. A[17:24]

　　WrNFAddr(addr>>16); //The 4th cycle of the write address, i.e. A[25].

　　WaitNFBusy(); //Wait for the system to be unbusy

　　for(i=0; i<512; i++)

　　buf[i] = RdNFDat(); //Loop to read 1 page of data

　　NFChipDs(); //Release NandFlash

　　}[page]

　　3. Write Operation Process

　　The write operation process is: 1. Send a write start command; 2. Send the first cycle address; 3. Send the second cycle address; 4. Send the third cycle address; 5. Send the fourth cycle address; 6. Write data to the end of the page; 7. Send a write end command

　　The following explains the reading and writing process by analyzing the code of the write page.

　　static void WritePage(U32 addr, U8 *buf) //addr indicates the page number in the flash, i.e. 'flash address >> 9'

　　{

　　U32 i;

　　NFChipEn(); //Enable NandFlash

　　WrNFCmd(PROGCMD0); //Send write start command '0x80'

　　WrNFAddr(0); //The first cycle of writing address

　　WrNFAddr(addr); //The second cycle of writing address

　　WrNFAddr(addr>>8); //The third cycle of the write address

　　WrNFAddr(addr>>16); Write address 4th cycle

　　WaitNFBusy(); //Wait for the system to be unbusy

　　for(i=0; i<512; i++)

　　WrNFDat(buf[i]); //Loop write 1 page of data

　　WrNFCmd(PROGCMD1); //Send write end command '0x10'

　　NFChipDs(); //Release NandFlash

　　}

　　IV. Conclusion

　　This article uses the S3C2410 processor and k9f1208 system as examples to describe the read and write process of nand flash. The bad block problem is not considered in the read and write process. The ECC and bad block processing issues will be described in the next topic.