Quick Start Technology of Single Chip Microcomputer

　　After the system is powered on or reset, the program starts to execute from the Reset Exception Vector at address 0x0, so the first instruction of the Bootloader needs to be placed here: b ResetHandler, jump to the ResetHandler label to perform the first stage of hardware initialization, the main contents are: turn off the watchdog timer, turn off interrupts, initialize PLL and clock, and initialize the memory system. After executing the above programs, the system initializes the stack and memory. The system stack initialization depends on which interrupts the user uses and which types of errors the system needs to handle. In general, the manager stack must be set, and if the IRQ interrupt is used, the IRQ stack must also be set. If the system uses peripherals, the relevant registers need to be set to determine their refresh frequency, bus width and other information.

　　The code segment is copied to RAM and executed

　　Because the code of embedded systems is usually solidified in ROM or Flash and starts running after power-on. Since the reading speed of ROM and Flash is relatively slow, this will undoubtedly reduce the execution speed of the code and the operating efficiency of the system. For this reason, the system code needs to be copied to RAM for running. Use the positioning information generated by the SDT linker ARMLink to move the valid code and data segments of RO to RAM. ARMLink links the compiled program into an ELF file. There are three output segments in the image file: RO segment, RW segment, and ZI segment. These three output segments contain read-only code and a small amount of data contained in the code segment, readable and writable data, and data initialized to 0. ARMLink also generates the start and end positioning information of these three output segments: Image$$RO$$Base, Image$$RO$$Limit, Image$$RW$$Base, Image$$Limit, Image$$Linit, and Image$$ZI$$ Limit. These positioning information can be used in the program. Move the code and data in ROM to RAM. The specific procedure is as follows.

　　LDR r0, =|Image$$RO$$Base| /*RO segment start address*/

　　LDR r1, =|Image$$RO$$Limit| /*RO segment end address*/

　　LDR r2, =|Image$$RW$$Base|

　　LDR r3, =|Image$$RW$$Limit|

　　/* Calculate the length of the code and data to be imaged respectively and add them up, and put them into register R1*/

　　SUB r1, r1, r0

　　SUB r3, r3, r2

　　ADD r1, r1, r3

　　/*Copy the code and data to be imaged into RAM*/

　　0 /*Identifier*/

　　LDR r3, [r0], #4

　　STR r3, [r2], #4

　　SUBS r1, r1, #4

　　BNE %B0 /*If the copying is not completed, jump to the assembly statement at the 0 identifier and continue copying. See the ARM instruction help manual*/

　　Create a secondary interrupt vector table

　　In the ARM system, the interrupt vector table is located at the address starting from 0X0, which means that no matter what upper-layer software is running, once an interrupt occurs, the program will get the interrupt vector table in the Flash memory, reducing the system's operating efficiency. Therefore, build your own secondary interrupt vector table in RAM. When an interrupt occurs, the program directly takes the interrupt vector from RAM and enters the interrupt subroutine. Especially in systems where interrupts occur frequently, this method can greatly improve the system's operating efficiency. The specific implementation code is as follows. [page]

　　b ResetHandler

　　b HandlerUndef /*Undefined mode handle*/

　　b HandlerSWI /*SWI interrupt handler*/

　　b HandlerPabort /*PAbort interrupt handler*/

　　b HandlerDabort /*Dabort interrupt handler*/

　　b. /*Reserved*/

　　b HandlerIRQ /*IRQ interrupt handle*/

　　b HandlerFIQ /*FIQ interrupt handler*/

　　HandlerFIQ HANDLER HandleFIQ

　　HandlerIRQ HANDLER HandleIRQ

　　HandlerUndef HANDLER HandleUndef

　　HandlerSWI HANDLER HandleSWI

　　HandlerDabort HANDLER HandleDabort

　　HandlerPabort HANDLER HandlePabort

　　HANDLER is a macro used to find the entry address of the interrupt handler. These addresses are stored in the table pointed to by HandleXXX, which is located at the high end of RAM and has a base address of _ISR_STARTADDRESS.

　　^_ISR_STARTADDRESS

　　HandleReset # 4

　　HandleUndef #4

　　HandleSWI # 4

　　HandlePabort # 4

　　HandleDabort # 4

　　HandleReserved # 4

　　HandleIRQ # 4

　　HandleFIQ #4

　　Applications of MMU

　　MMU is the abbreviation of memory management unit, which is a device used to manage the virtual memory system. MMU is usually part of the CPU and has a small amount of storage space to store the matching table from virtual address to physical address. This table is called TLB (Translation Lookaside Buffer). All data requests are sent to the MMU, which determines whether the data is in RAM or in a large-capacity external memory device. If the data is not in the storage space, the MMU will generate a page fault interrupt. The structure of the MMU memory system allows fine control of the memory system, and most of the control details are provided by the translation table stored in the memory. The entries of these tables define the properties of various memory areas from 1KB to 1MB. The two main functions performed by the MMU are: converting virtual addresses into physical addresses and controlling memory access permissions. When the MMU is turned off, the virtual address is directly output to the physical address bus.

　　Through the above analysis, it can be found that the system startup program mainly completes the hardware initialization, overcomes the weakness of slow Flash or ROM reading speed, improves the reading speed of instructions and data, realizes high-speed operation of the system, and reduces the use of RAM and system costs through the application of MMU.