PIC Microcontroller Study Notes

1. Status register STATUS

2. Implement indirect addressing registers INDF and FSR

3. Registers PCL and PCLATH related to the program counter PC

4. Power control register PCON

PIC microcontroller instruction system

PIC16F87X has 35 instructions, all of which are single-byte instructions with a length of 14 bits. All instructions are divided into three categories according to the operation objects: byte-oriented operation category (17 instructions); bit-oriented operation category (4 instructions); constant operation and control operation category (14 instructions).

PIC Configuration Word Settings

So far, I have learned two methods of setting the configuration word of PIC:

1. Two "_"s follow CONFIG, followed by the value after the configuration word is set;

2. Two "_"s follow CONFIG, followed by the bits and states of each configuration word. The format is as follows:

;==============================================

; Configuration word definition

;==============================================

__CONFIG _DEBUG_OFF&_CP_ALL&_CPD_ON&_LVP_OFF&_BODEN_OFF&_PWRTE_ON&_WDT_OFF&_HS_OSC ;配置字定义

Indirect Addressing, INDF and FSR Registers

The INDF register is not a physical register, and addressing the INDF register will result in indirect addressing. [page]

Indirect addressing is achieved using the INDF register. Instructions to any INDF register actually access the register pointed to by the pointer register FSR. Indirect reads of the INDF register itself return 00H. Writing to the IDNF register using indirect addressing will result in a no operation (although the status bits may be affected). The effective 9-bit address is obtained by combining the 8-bit FSR register and the IRP bit (STATUS<7>). An example is as follows:

Indirect addressing example:

Example: Write 30H~7FH to the 30H~7FH units in sequence. COUNT is the counting register.

;==============================================

; Continuous address write data subroutine (indirect addressing)

;==============================================

WR_ADS: MOVLW 30H; Initialize the RAM contents as follows

MOVWF FSR ; Start from unit 30H

MOVLW 30H ; assign value 30H to unit 30H

MOVWF COUNT ;

INTRAM: MOVF COUNT,0; assign 30H～7FH to unit 30H～7FH

MOVWF INDF ; Operate on INDF

INCF COUNT,1 ;COUNT+1

INCF FSR,1 ; pointer +1

BTFSS COUNT,7; Is COUNT<7> 1? (When 7FH, COUNT<7>=0)

GOTO INTRAM ;

RETURN ;Program returns

PIC microcontroller register definition

When programming a PIC microcontroller, you need to define the registers you need in the program. Usually, pseudo instructions are used. However, the following method can be more convenient.

Use CBLOCK followed by the address of the register to be defined. You can define multiple registers together, in which case the register address will be automatically assigned to the next address. Use ENDC to complete the definition.

Here is an example:

;================================================

; Space definition

;=================================================

CBLOCK 20H; defined from 20H

COUNT; address is 20H

W_TEMP; address is 21H

STATUS_W; address is 22H

ENDC ; End definition

PIC microcontroller I/O operation

By setting a bit in the TRISX register to 1, the corresponding output driver can be placed in high-impedance mode. By clearing a bit in the TRISX register to 0, the contents of the output latch are latched to the specified pin.

RCSTA register operation precautions

During the data reception process, if the received data is read out in time, the USART will normally receive the next data sent. However, if an interrupt occurs during reception, or other operations that interrupt reception delay the timely reading of the data in RCREG. At this time, the shift register will no longer put any data into RCREG. In this case, even if there is data to be sent, the RCIF flag will not be set, and the reception will be interrupted. If no measures are taken, the communication will be completely interrupted.

The reason for this problem is that the above operation interrupts the reception and delays the timely retrieval of data, causing the overflow flag OERR (RCSTA<1>) in the RCSTA register to be set. When this flag is set, the shift register is prohibited from putting the received data into RCREG, making it impossible to continue receiving.

The solution to this problem is to clear OERR. Clearing OERR cannot directly operate on this flag bit. You must clear the overflow error flag OERR by clearing the continuous reception enable bit CREN (RCSTA<4>). However, after clearing the continuous reception enable bit CREN (RCSTA<4>), you must set this bit again, otherwise, only one byte can be received.