HDLC protocol chip PT7A6525 and its application in switches

1 Overview
HDLC protocol does not rely on any character encoding set; data messages can be transmitted transparently, and the "0-bit insertion method" used to achieve transparent transmission is easy to implement in hardware; full-duplex communication, data can be sent continuously without waiting for confirmation, and has high data link transmission efficiency; all frames use CRC checksum, and the information frames are numbered sequentially to prevent leakage or retransmission, and the transmission reliability is high; the transmission control function is separated from the processing function, which has greater flexibility.
The author has written an article introducing MT8952B and received many inquiries from readers on related issues. With the continuous development of electronic technology, the switching capacity requirements of switches are getting higher and higher, and the communication volume is also increasing. The MT8952B with 19-byte FIFO can no longer meet the needs of users. The HDLC chip has a 64-byte FIFO, and the transmission information can be unrestricted. The PT7A6525 HDLC protocol controller has the following features: supports 2 completely independent full-duplex HDLC channels, compliant with X. 25 second layer standard data format, forward sequence generation and detection, single byte address recognition, microprocessor port, flexible operation and control register, 64 bytes of FIFO buffer for sending and receiving, multi-channel data link handshake signal, high-speed serial clock output (8 Mbps), programmable channel selection and time slot control in accordance with ST-BUS, flexible protocol control function, low power consumption ISO-CMOS technology. Its main application areas include: data link control and protocol generation, digital equipment, PBXs and dedicated data networks, D channel controller of ISDN basic data, C channel controller of data network interface circuit, internal communication processing, etc. The internal structure of PT7A6525 is shown in Figure 1.

2 PT7A6525 Registers
The PT7A6525 HDLC protocol controller processes the protocol structure and frame data defined by the packet exchange protocol X.25 (Layer 2) recommended by CCITT. Transparency of data transmission is achieved through zero bit insertion and deletion technology. In the process of sending data, the HDLC frame flag (OllllllO) and FCS (Frame Check Sequence) frame check sequence field, as well as frame abnormal termination, channel idle and other receiving states are automatically generated, so that the PT7A6525 automatically forms an HDLC frame with the data to be sent. At the receiving end, the HDLC frame from the remote end is FCS-checked and the original data is restored.
The PT7A6525 has two ports: one is a serial port for sending and receiving data packets; the other is a parallel port that allows parallel data transmission between the microcontroller system bus and the protocol processor. This interface includes data bus (D0~D7), address bus (A0~A6), clock, chip select (CS) and read/write control, etc. The microprocessor can read/write various registers of the protocol processor. Table 1 gives the addresses of these registers. For a detailed description of the registers, refer to the PT7A6525 data sheet.

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3 PT7A6525 Clock Mode
The clock modes supported by each channel of PT7A6525 include internal clock crystal (OSC) mode, independent baud rate generator (BRG) and digital pulse phase-locked loop (DPLL) mode. The receiving and transmitting clocks can be generated by setting registers: internal clock generation can be obtained through OSC, BRG and DPLL, and external clock can be obtained through TxCLK/RxCLK. In short, 8 different clock modes can be generated through software settings of channel configuration register 1 (CCR1), as listed in Table 2.

This article takes external clock mode O as an example for detailed introduction. It is mainly applicable to point-to-point or point-to-multipoint connections, and is synchronized with the transmit and receive pins respectively.

4 PT7A6525 Application in Switches Connection Diagram
The example given in this article is the communication between a single board and a main network, which adopts serial HDLC communication in point-to-multipoint and master-slave mode. The connection block diagram is shown in Figure 2. The HDLC controller of the main network control board is the master, and the HDLC of other boards is the slave. The HDLC of the main network control board polls other boards according to the address, and only the polled board can respond.
The receiving line of the board is connected to the HDLC controller through the driver. The sending line of the board is sent to the backplane after being driven. The output of this driver is controlled by the logic of the board, and the specific control is divided into several situations: a. When power-on reset, the logic control is high-impedance output. b. When the MCU crashes, it causes a reset and is also controlled to high-impedance output to prevent the board from occupying the bus for a long time. c. When polling this board, the board enables the output before sending data, and then sets it to high impedance after sending, giving up the bus.
The HDLC controller of the single board uses the dual-channel HDLC chip PT7A6525 introduced in this article, which is directly connected to the HDLC chip (such as PT7A6632 for the main network control layer). A6~A0 are the register address selections of the protocol controller. The microcontroller can read/write these registers, and the serial port can transmit/receive data packets, and can also be connected to digital transmission media or digital interface circuits, such as MT8972, MT8980, etc. For example, TxD and RxD can be connected to the bus of MT8980.

5 PT7A6525 data read/write application example
According to the previous introduction, the application connection diagram in Figure 2 (the specific interface diagram can be referred to the chip manual, etc.) can control the register to achieve the desired purpose. In actual application, the article gives an example of the point-to-point mode reading and sending data subroutine for reference.

5.1 Reading Data
The reading of PT7A6525 data is realized in the external interrupt. When data arrives, INT is pulled low and the microprocessor generates an interrupt, which can be operated in the external interrupt service program.

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In actual applications, the received data may be incorrect. In this case, you can read the external interrupt register receive overflow flag. If it is 1, read the data and discard it. If the number of bytes of the data to be sent is uncertain, you can judge the receive FIFO end flag in the FIFO status register, so that the correctness of the data can be ensured.
5.2 Sending data
PT7A6525 can send data in an interrupt or during program execution. Assume that the data to be sent is placed in the buffer t_pt7a6525[MSG_LEN]. In the following example, the message length MSG_LEN is very flexible and can be any value, and more than 32 bytes can be sent. Note that a maximum of 32 bytes can be sent each time. When the last sent data is less than 32 bytes, write 1 to the XTF and XME bits of the command register to indicate that the data packet has been sent.

6 Application of PT7A6525 in program-controlled digital switches
In program-controlled digital switches, the most widely used is the transmission and reception of switching signaling. The microprocessor performs corresponding operations according to the received signaling or message. For example, if a SETUP message is received, a SETUP ACKNOWLEDGE needs to be sent. Then, according to different messages, different voice connections, voice connections, circuit control, etc. are performed. In the application of program-controlled digital switches, especially standard signaling such as No. 7 and DSS1 signaling, the communication volume between offices is large, and a protocol discriminator (protocol discriminator) usually requires 32 bytes or more. This article gives a message establishment (SETUP) example in the Q. 931 protocol discriminator for reference.
The Q. 931 protocol stipulates that each message must contain a protocol discriminator (protocol discriminator), a call reference (call reference), a message type (message type), and other information elements (0 other information elements, as required), as shown below: