A Brief Discussion on the RETI Instruction of 51 Single Chip Microcomputer

Recently, a very strange problem occurred in the process of programming based on 51 single-chip microcomputers: "During the program execution, under the conditions of register EA=1, ET0=1, and TR0=1, the interrupt was not executed when TF0=1". Those who have experience in single-chip microcomputer interrupt programming know that when EA=1, ET0=1, and TF0=1 is satisfied, if there is no higher priority interrupt execution during this period, timer interrupt 0 will definitely generate an interrupt response. In the program I wrote, only timer interrupt 0 was used, and there was no priority problem for an interrupt. After checking my own program and comparing the interrupt programs in various textbooks, I found a problem in my program: due to the uncontrollability of the interrupt, it is uncertain to jump out of the interrupt and return to the main program, and because the program needs to jump to the specified address after the interrupt jumps out. In order to solve this problem, I directly used the unconditional jump instruction "LJMP ADR16" at the end of the interrupt, where ADR16 is the address where I want the program to run after the interrupt ends, without passing through the instruction "RETI". The problem was found, which means that the difference between my program and other programs is that it does not execute "RETI" but jumps out directly.

In order to solve the problem, I consulted a lot of information and textbooks on single-chip microcomputers. Almost all textbooks have the same definition of the role of the instruction "RETI": "After the interrupt program is completed, a RETI instruction must be executed. After executing this instruction, the CPU will take out the address stored in the stack and send it back to the PC, and then the program will continue to execute from the interruption point of the main program." If the role of "RETI" is only to "take out the address stored in the stack and send it back to the PC"; then can't I achieve the same effect of pushing the address by replacing it with the two instructions "POP DPH" and "POP DPL"? This can solve the stack overflow error caused by only pushing the stack instruction (automatically generated by the hardware) without popping the stack, but it cannot solve the "cannot enter the interrupt" problem mentioned at the beginning of the article. This makes me more convinced that the role of the instruction "RETI" introduced in the book is not complete. After consulting various materials and documents, I found a concept of "'priority effective' trigger" that was not mentioned in the textbooks and teachers when introducing single-chip microcomputer hardware and registers. The data points out that "according to the structural characteristics of 8051, its interrupt system contains two non-addressable "priority effective" triggers. One is used to indicate whether the CPU is executing a high-priority interrupt service program. When this trigger is 1, the system will block all interrupt requests; the other indicates whether the CPU is executing a low-priority interrupt service program. When this trigger is 1, it will block all interrupt requests except for high-priority ones. It can be seen that if you want to respond to interrupt requests of the same level or even lower level, you must clear the "priority effective" trigger. But this trigger is not addressable, so it cannot be cleared directly by software." Is the problem here? How is the "priority effective" trigger cleared? It is automatically executed by the hardware, so when is it executed? I will solve the problem with the problem. Suppose I can make the program jump to the original specified address "ADR16" after jumping out of the interrupt and satisfy the execution instruction "RETI". After repeated thinking, I used four instructions: "DEC SP"; "DEC SP"; "MOV DPTR, #ADR16"; "PUSH DPL"; "PUSH DPL" and "PUSH DPH" to replace them, and the problem was solved.

Summary: The interrupt instruction "RETI" as an interrupt jump instruction not only takes out the address stored in the stack and sends it back to the PC, so that the program can continue to execute from the interruption point of the main program, but also clears the "priority effective" trigger. This error also occurred in the program I made. Due to the clearing of the "priority effective" trigger, the second interrupt could not be entered (equivalent to the same priority application).

Postscript: The knowledge I used to solve this problem was from the textbook, but not entirely from the textbook. In this process, I used the knowledge I had learned to solve my own problem, and further introduced some new knowledge of the interruption process. I believe that the learning of new knowledge depends largely on the acquisition of new knowledge through the process of application, summary, deduction, etc. on the basis of the knowledge I have learned. This is also an ability of contemporary college students to apply knowledge and acquire new knowledge.