Research on Functional Simulation Verification Based on 82C52

1 Introduction

Functional simulation mainly verifies the correctness of the circuit function being verified, and is mainly divided into RTL level simulation and netlist simulation. Netlist is further divided into DC output and As output. Since neflist simulation comes with sdf file (delay information), it is more accurate than RTL simulation, and the closer to the back end of the process, the more realistic the simulation delay information is, and the closer the simulation result is to the actual situation.

2. Determination of verification scheme

The verification scheme designed this time is implemented based on the control of the external serial port circuit by the microcontroller. The basic block diagram of the verification scheme is shown in Figure 1.

Figure 1 82C52 test platform

3 Files to be prepared for simulation

RTL (Pre sire): testbench (simulation stimulus), Design (simulated design) DC_ netlist: testbench (simulation stimulus), Design (simulated design), saf (delay information, written by DC), SimulatiONlibrary

Astro_netlist (post sim): testbench (simulation stimulus), Design (simulated design), Sdf (delay information, written by), Simulation library

The main tool for simulation is VCS, and the main command is: >VC$testbeneh．v design．v—RI—M. At the same time, code coverage analysis is also required. Since the testbench coverage written at the beginning is definitely incomplete, it is necessary to continuously improve it later to improve the code coverage to meet the design requirements. The main command for code coverage analysis using VCS is: add the option cmline+tsl+FSM+eond during compilation, which are four coverages. You can choose only one or several of them according to your needs; VCS—cm—PP gui to view the coverage results.

4. Testbench writing

Connect 82C52, 8032 and some peripheral interface circuits together to form a simple system, and use the assembly program to control 82C52 to achieve the purpose of simulation. Therefore, the writing of testbeneh is mainly to complete the construction of this simple system, and read the pre-programmed single-chip assembly instructions. [page]

5 82C52 Functional Description

(1) Reset

After power-on, the reset input is high, and the 82C52 is initialized within two 1x clock cycles and enters idle mode until the program is written.

When the reset input is high, the clock counter and bit counter of the internal baud rate generation circuit are reset. BRSR is not affected (except the 7th bit); USR is cleared (except TC and TBRE); MCR is cleared; all discrete signals, memory units and various logic register bits are cleared and turned off. Then the reset state is cleared (RST=0), and the 82C52 remains in idle mode until the program is written.

During simulation, first verify the correctness of Reset:

Hardware Reset: After power-on, the Reset input of the 82C52 must maintain a high level for at least two clock cycles to initialize the 82C52 and put it into idle mode. The operations caused by the reset are:

① Reset the clock count and bit count of the internal baud rate generator, and reset the seventh bit of the Band Rate Select Register (BRSR) to 0. In @USR, except for TC and TBRE, the remaining bits are cleared, MCR is cleared, and other related memories and registers are also cleared or set to invalid. However, it should be noted that the reset does not affect the UCR. After the reset, the idle mode will remain until the 82C52 is programmed to change its mode. This reset does not affect the BRSR and UCR.

Software Reset: First, read the data in USR and RBR to clear the residual data and status to avoid concurrent or repeated control, and then restore the 82C52 to the idle state by setting the values ​​of the three registers UCR, BRSR, and MCR.

(2) Programming

The registers that need to be set before programming are BRSR, MCR and UCR to initialize 82C52, but note that MCR should be set last.

UCR: Set the frame format, DO bit sets the number of stop bits, when DO=0, the stop bit is 1 bit, when DO=1, if the data is 8 bits, the stop bit is 1.5 bits, the data bit is 5 bits, the stop bit is 1 bit, the data bit is 6 or 7 bits, the stop bit is 2 bits. D3, D2, D1 bits set the parity bit. D5, D4 are for setting the number of data bits, 00=5bits, 01=6bits, 10:7bits, 11=8bits. The highest two bits are reserved and set to 0.

BRSR: Set the baud rate, D1 and Do bits control the first frequency division, 00=/1, 01=/3, 10=/4, 11=/5, D6 to D2 bits control the second frequency division, there are 18 kinds of frequency division, so there are 72 frequency division methods in total, the frequency after two divisions is 16 times the frequency finally used by 82C52.

MCR: can select the working mode, interrupt control, receive and send request and other commands of 82C52. DO is the request to send control bit, which is low effective. D1 is the terminal ready control bit, which is low effective. D2 is the interrupt enable control bit, 1 is interrupt enable. D5 is the receive enable control bit, 1 is receive enable, and this bit is set to invalid (0) during software reset. D6 is the terminal interrupt enable control bit, 1 is interrupt enable. D7 must be set to 0 to ensure that 82C52 is set normally. D3 and D2 are mode selection control bits, 00=Normal, 01=Transmit Break, 10=Echo mode.

At this point, the settings before programming 82C52 are completed, and these settings are completed through assembly instructions. The registers related to receiving and sending are RBR and TBR, which are bitO to bit7 from DO to D7. When the number of data bits is less than 8, the other high bits in RBR except the valid data are set to 0, and those in TBR are ignored.

The data of SDI enters the receiving register serially and then enters the receiving buffer register in parallel, and then the DR output terminal and the flag DR in USR are set. The state of TRB is marked by the TBRE output terminal and the flag TBRE in USR, and when TRB and TC are both empty, it is marked by the TC flag in USR.

USR: UART status register. The data in this register can be cleared by the CPU reading and maintained until the status changes again.

MSR: Terminal Status Register.

After programming is completed, 82C52 will be ready to perform communication functions.

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The control registers can be written to with any command. The MCR is written last because it controls the interrupt enable, remote device control output and receive enable bits. Once the 82C52 is programmed and operational, these registers immediately send or receive data. Table 1 shows the control signals for the 82C52 internal registers.

Table 1 Control signals of 82C52 internal registers

82C52 interrupt structure:

82C52 has an interrupt output pin, and there are two control bits in MCR: MIEN and INTEN. If these two flag bits are set to invalid, no interrupt will be caused. If MIEN is invalid and INTEN is valid, the signals that cause interrupts are RBRK, TC, OE, FE, PE (check the rising edge at this time). If both are set to valid, the signals that cause interrupts in addition to the above are DSR\ and CTS\ (both rising and falling edges are valid).

The conditions under which the 82C52 may interrupt are:

(1) The SDI pin receives data (RBRK??).

(2) Sending data completed (TC).

(3) An error occurs when receiving data and an error message is generated (OE, FE, PE).

(4) The terminal control signal changes (DSR\, CTS\).

The functions of each part above can be verified one by one by programming 8032. During verification, the output data is saved and compared with the input data. If it is correct, it can be passed. If it is incorrect, it can also be located which register or data is wrong.

6 Conclusion

I think that general simple interface circuits can be verified by controllers similar to single-chip microcomputers. In this way, the stimulus can be given by the controller, and there is no need to consider whether the timing relationship of the stimulus is correct, which is simple and convenient.