Function and application of PCI9052 interface circuit

1 Introduction

The PCI (Peripheral Component Interconnect) bus has the characteristics of being independent of the processor, high data transfer rate, plug-and-play, low power consumption, and strong adaptability, and has become the mainstream bus for microcomputers. The CompactPCI and PXI buses formed based on the PCI bus are widely used in the fields of instruments and automation. With the widespread application of the PCI bus, the design and development of its interface is particularly important. Due to the unique performance of the PCI bus, such as signal load capacity, support for burst transmission of data, address/data, command/byte enable signal bus multiplexing, etc., it is difficult for small and medium-sized devices to implement interface circuits. To implement the PCI bus interface, CPLD or FPGA is generally used to design the PCI interface, which is very difficult; another method is to use a dedicated PCI interface circuit to exempt designers and developers from tedious timing analysis, shorten the development cycle, and reduce development costs. This article introduces the functions of the PCI9052 interface circuit and its application in PCI board design.

2 Interface Circuit

PCI9052 is a low-cost PCI bus target interface circuit developed by PLX. It has low power consumption, uses a PQFP 160-pin package, and complies with PCI2.1 specifications. Its local bus (LOCAL BUS) can be programmed as an 8/16/32-bit (non-) multiplexed bus, and the data transfer rate can reach 132Mb/s. It provides an ISA interface, which allows ISA adapters to be quickly and cost-effectively converted to the PCI bus. The main functions and features are as follows:

Asynchronous operation. The clocks of the PCI9052 Local Bus and PCI bus run independently. The asynchronous operation of the two buses facilitates the compatibility of high-speed and low-speed devices. The operating clock frequency range of the Local Bus is 0MHz to 40MHz, TTL level, and the operating clock frequency range of PCI is 0MHz to 33MHz.

Support burst operation. PCI9052 provides a 64-byte write FIFO and a 32-byte read FIFO to support pre-fetch mode, i.e., burst operation.

Interrupt generator: A PCI interrupt signal INTA# can be generated from the two interrupt signals LINTi1 and LINTi2 of the Local Bus.

Serial EEPROM interface, used to store the configuration information of PCI bus and Local bus.

5 local bus address spaces and 4 chip selects, base address and address range can be programmed by serial EEPROM or master device.

There are two ways to swap the byte order in big/little Endian mode.

Bus driver: All address, data and control signals are directly driven by PCI9052 without additional driver circuit.

Localbus wait state. In addition to the wait signal LRDYI# for handshake, PCI9052 also has an internal wait generator (including waits for address to data cycle, data to data cycle and data to address cycle).

PCI locking mechanism: The master device can obtain the sole access to PCI9052 through the locking signal.

ISA bus mode. PCI9052 provides an ISA logic interface, users can directly connect the PCI bus and ISA bus, and can easily convert ISA design to PCI.

The interface diagram of PCI9052 is shown in Figure 1.

Figure 1 PCI bus interface diagram

3 PCI9052 Functions and Operations

3.1 Initialization

When powered on, the RST# signal of the PCI bus sets the internal registers of the PCI9052 to the default values. At the same time, the PCI9052 outputs a local reset signal (LRESET#) and checks whether the EEPROM exists. If the device is equipped with an EEPROM and the first 16 bytes of the EEPROM are not empty, the PCI9052 sets the internal registers according to the EEPROM contents, otherwise it is set to the default values.

3.2 Reset

PCI9052 supports two reset modes: hardware reset and software reset. Hardware reset means that when the RST# signal input of the PCI9052 bus interface is valid, the entire PCI9052 will be reset and the LRESET# local reset signal will be output. Software reset means that the host on the PCI bus can reset the PCI9052 by setting the software reset byte (Bit30) in the control register CNTRL (50H) and output the LRESET# signal. At this time, the values ​​of the configuration registers of the PCI and local buses will remain unchanged. When the software reset byte in CNTRL is valid, PCI9052 only responds to access to the configuration register and does not respond to access to the local bus. PCI9052 remains in this state until the host on the PCI bus clears the software reset byte.

3.3 Access to the Serial EEPROM Interface

After reset, PCI9052 starts to read the serial EEPROM. If the first word read is not FFFFH, PCI9052 considers that there is a valid EEPROM and continues to read. Otherwise, the EEPROM is considered invalid. The master device of the PCI bus can read and write the serial EEPROM connected to PCI9052. Before reading or writing, it is necessary to set the control register CNTRL[25] (enable bit) to "1" and control the CNTRL[24] bit to generate the clock of the serial EEPROM. Then, send the instruction code from EEDI. If EEDO outputs "0" after the instruction code, it means that it can be read or written. When you need to end the operation, just set CNTRL[25] to "0".

3.4 Access to internal registers

PCI9052 provides two types of on-chip registers, namely PCI configuration registers and local configuration registers. Both can only be accessed by the PCI bus and serial EEPROM. Access to the latter can also be prohibited by setting register CNTRL[13:12]. This greatly enhances the flexibility of interface design.

3.5 Direct Data Transfer Mode

PCI9052 supports direct access of the host processor on the PCI bus to the devices on the local bus. The configuration register of PCI9052 maps the access to the local address space. The on-chip read and write FIFO memory enables PCI9052 to support high-performance burst transmission between the PCI bus and the local bus. The schematic diagram of the PCI bus master accessing the local bus is shown in Figure 2.

Figure 2 PCI master direct access local schematic diagram

3.6 Generation of PCI Interrupt (INTA#)

To generate PCI interrupt INTA#, first set register INTCSR[6] (PCI interrupt enable bit) to "1". If you need to generate an interrupt in software mode, just set INTCSR[7] (software interrupt bit) to "1". If the system design uses the method of generating interrupt signals INTi1 and INTi2 from the devices on the local bus and then generating PCI interrupt INTA#, just set the relevant bits of register INTCSR according to Table 1. After reset, the value of INTCSR will all be "0". [page]

Table 1 Register INTCSR related settings

4 Application Examples

PCI9052 is a very powerful PCI interface circuit. Using it to design PCI adapter cards will make the interface very convenient. Figure 3 is a schematic diagram of the interface for the PCI host processor to read SRAM. Its main function is to implement single or burst read and write operations on RAM.

4.1 Circuit Connection

According to the connection circuit in Figure 3, there are mainly the following pins for SRAM: A (17, 0), I/O (7, 0), OE, CE, WE, etc. The address line A (17, 2) is connected to the local address line LA [17, 2]. According to the definition of LBE [0, 3] # of PCI9052, an 8-bit data bus is used here to connect LBE0 # to A0, LBE1 # to A1, and OE to CS0 # of PCI9052. PCI9052 provides designers with 4 chip select signals CS (3: 0) #, which can provide chip select signals for 4 devices. In this way, designers can avoid designing chip select decoding circuits when designing circuits. Its address and range can be configured by its corresponding internal local register. Serial EEPROM is used to store configuration information in the configuration register, and NM93C46 or compatible memory can be used.

4.2 Register Settings

After the circuit is connected, the internal registers of PCI9052 must be configured to make the circuit work properly. According to the performance and characteristics of the circuit, the registers should be set to non-multiplexed working mode, memory mapping, and 8-bit data bus. The base address register value of local bus 0 is 240001H, its address range register value is 3FFF8H, and its description register value is 39H; the initial value of chip select 0 base address register is 4C0001; the initial value of the command register is 02H; the initial value of the status register is 800H, and other registers use the default value. After determining the value of each register, the initial value of the register should be written into the EEPROM in a certain order.

4.3 Driver Development

In order to obtain the mapping base address dynamically allocated by the host from the PCI bus configuration register and read and write the mapped port, a driver must be written. When writing Windows drivers, you can use DDK, but it is more difficult. In order to simplify driver development, you can use the WinDriver development tool launched by Jungo. WinDriver can automatically generate VxD drivers and corresponding high-level functions. Users do not need to have knowledge of Windows driver development, and the generated high-level functions can be directly called in high-level programming languages ​​such as VC or CBuilder.

5 Conclusion

Practical proof, the use of dedicated PCI interface circuit brings great convenience to the design of PCI interface card. This article mainly introduces PLX's PCI9052 dedicated interface circuit, designers can choose other interface circuits according to needs, when ISA interface is not needed, PCI9050 can be selected; when DMA data transmission is required, PCI9054 can be selected. Dedicated interface circuit is the best way to design PCI adapter card, which not only greatly shortens the design cycle, but also facilitates the development of driver.

References
[1] Li Guishan, Qi Dehu. PCI Local Bus Developer's Guide [M]. Xi'an: Xi'an University of Electronic Science and Technology Press, 1997.
[2] Yang Quansheng, Hu Youbin. Modern Microcomputer Principles and Interface Technology [M]. Beijing: Electronic Industry Press, 2002.
[3] Tom Shanley, Don Anderson, Liu Hui, translator. PCI System Architecture [M]. Beijing: Electronic Industry Press, 2000.