Interface technology between SSD1906 display controller and AT91RM9200-EEWORLD

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introduction

SSD1906 is a small-to-medium-scale display control chip launched by Solomon. This display control chip integrates video memory and timing circuits, thus providing a low-cost, low-power single-chip solution for handheld devices and consumer electronics. AT91RM9200 is an embedded processor based on ARM9 launched by Atmel, with a clock frequency of 180MHz.

The AT91RM9200 processor does not have an integrated LCD controller, so a dedicated display controller is needed to realize LCD display. This article introduces the specific application of SSD1906 display controller in embedded systems based on AT91RM9200 microcontroller.

1 SSD1906 Display Controller Introduction

The SSD1906 display control chip integrates 256KB of SRAM video memory, which can support monochrome and color LCDs, as well as a variety of active and passive panels. The SSD1906 also has strong bus compatibility and can be connected to various types of MCUs. In addition, the functions provided by the SSD1906 also include virtual display, floating window (variable window size) display, and support for two cursors, which can reduce software operations. The 32-bit internal data channel can provide high-bandwidth display memory to achieve fast screen refresh. The SSD1906 also has the advantage of single voltage power supply.

Another feature of the SSD1906 display controller is that it has a very short CPU access delay time, so it can support microprocessors without READY/WAIT interactive signals. In addition, the SSD1906 supports single clock signal input, that is, the bus clock (BCLK), memory clock (MCLK) and pixel clock (PCLK) can all be obtained from the clock input CLK1. This display controller has no specific requirements for the type of MCU and operating system, so it is an ideal display solution in practical applications. The display control system structure based on SSD1906 is shown in Figure 1.

1.1 Bus compatibility

The SSD1906 display controller is compatible with various types of MCU interfaces, especially for currently commonly used embedded processors, which can basically achieve seamless connection. For different bus interfaces, SSD1906 provides multiple timing control registers, which can be configured accordingly according to the timing requirements of different interfaces. The MCU bus interface types supported by SSD1906 include: Universal #1 and Universal #2 bus interfaces with WAIT signals; Intel StrongARM/Xscale; Motorla MX1 Dragon Ball; Motorola MC68K; Motorola Dragon Ball MC68ez328/MC68VZ328; Hitachi SH3 and SH4.

In addition to supporting 16-bit and 32-bit processors, SSD1906 can also support 8-bit processors. SSD1906 integrates 256KB of video memory and supports register mapping in memory; through the M/R input signal, choose to access the memory address space or the register address space. In addition, through the 18-bit address bus, the MCU can directly access the continuous 256KB video memory inside the SSD1906.

1.2 Display support and display mode

The SSD1906 display controller supports multiple types of LCD interfaces, including 4/8-bit monochrome STN interface; 4/8-bit color STN interface; 9/12/8-bit active matrix TFT interface. In addition, the SSD1906 supports four color depths of 1/2/8/16bpp. For monochrome passive LCD panels, the SSD1906 also has 64 gray levels; for both passive STN panels and active matrix TFT panels, the SSD1906 can support up to 256K colors. In addition, the SSD1906 also supports multiple resolutions, including 320×320, 160×160 and 160×240 (with a color depth of 16bpp).

1.3 Display characteristics

In terms of display characteristics, SSD1906 supports display rotation mode. By setting the corresponding control registers inside SSD1906, the displayed image can be rotated by 90°, 180° and 270° hardware. At the same time, SSD1906 also supports virtual display, that is, the displayed image size can be larger than the actual selected LCD panel. Users can scroll the screen up and down and left and right to view the complete image.

The SSD1906 display controller supports floating window display mode. In this mode, a floating window can be displayed in the main display window at the same time. This floating window can be located at any position in the main window, which can be set through the floating window control register. In addition, the SSD1906 also supports two hardware cursors (only supports 4/8/16bpp) and supports double buffer/multi-page mode, so it can display smooth animations and achieve real-time screen refresh.

2 AT91RM9200 microcontroller

Atmel's AT91RM9200 is an ARM920T microcontroller based on ARM Thumb, with a clock frequency of 180MHz and an operating speed of up to 200MIPS. The AT91RM9200 has 16KB of data cache and instruction cache, and a memory management unit (MMU). In addition, the AT91RM9200 also includes 16KB of SRAM and 128KB of ROM, and has an external bus interface (EBI), supporting SDRAM, static memory, Burst Flash, CompactFals, SmartMedia, and NAND Flash.

The system peripherals provided by the AT91RM9200 microcontroller include: an enhanced clock generator and power management controller; two on-chip crystal oscillators with dual PLLs, a low-clock operating mode, and power optimization functions implemented by software; four programmable external clock signals; system timers including timer interrupts, watchdog, and a second counter; a real-time clock with an alarm interrupt; a debug unit, a two-wire UART, and support for debug communication channels; an advanced interrupt controller with eight priorities, independently maskable vector interrupt sources, and spurious interrupt protection; seven external interrupt sources and one fast interrupt source; four 32-bit PIO controllers, up to 122 programmable I/O lines, each with an input change interrupt and an open-drain capacitor; and a 20-channel peripheral data controller (PDC).

3 Hardware Design

3.1 Bus interface of SSD1906

The SSD1906 display control can be connected to a variety of MCUs. The specific connection method depends on the bus type supported by the MCU. The SSD1906 supports a single clock input (CLKI), so that the MCU's bus clock can provide it with a clock signal. For the universal #1 bus, the pins used by the SSD1906 to connect to the MCU are:

A0——connect to low level;

A[17:1]——System address bus bits 17 to 1;

D[15:0]——System data bus input;

WE0——Write enable signal input for lower 8-bit data;

WE1——Write enable signal input for high 8-bit data;

CS——Chip select input;

M/R——Select to read or write display memory or internal register. High is display memory, low is internal register;

BS——connect to high level;

RD/WR——Read command input for high 8-bit data;

RD——Read command input for lower 8-bit data;

WAIT——Wait for signal output. The signal can be configured to be high level effective or low level effective;

RESET——Reset input signal.

3.2 Bus interface analysis and implementation

The bus interface of the AT91RM9200 microcontroller belongs to the universal #1 type interface, so it can be directly connected to the SSD1906. Among them, the A[17:1], D[15:0], NWR0, NWR1, NCS2, NWAIT, and NRST pins of the AT91RM9200 can be directly connected to the A[17:1], D[15:0], WE0, WE1, CS, WAIT, and RESET pins of the SSD1906 respectively. The NRD pin of the AT91RM9200 can enable 16-bit or 8-bit read access, so it can be connected to the RD/WR and RD pins of the SSD1906 as the read enable signal for the high byte and low byte. The M/R signal of the SSD1906 can be controlled by the A18 signal of the AT91RM9200. The bus connection between the SSD1906 and the AT91RM9200 is shown in Figure 2. [page]

In addition, since the maximum input clock frequency of CLKI of SSD1906 is 66MHz, and the maximum bus clock frequency is also 66MHz, the bus clock BCLK of SSD1906 can be directly provided by CLKI, and the frequency ratio is 1:1. In addition, the bus type of AT91RM9200 is general #1 type, the NWAIT signal is selected as low effective, and the bus interface is in little end mode, so it can be determined that the configuration pin CF[7:0] of SSD1906 is 0x0Bh.

4 Register Configuration

In terms of register configuration, it includes the initialization of MCU and the initialization and setting of SSD1906. For the AT91RM9200 microcontroller, first, the corresponding PIO control register must be set to configure the multiplexed I/O lines to the required functions. Secondly, considering that the maximum CLKI clock frequency of SSD1906 is 66MHz, it is necessary to set the PMC_PCK0 register of AT91RM9200 to ensure that the output clock frequency of PCK0 does not exceed 66MHz. The main register configurations of SSD1906 are introduced below.

4.1 Internal clock settings of SSD1906

SSD1906 supports single clock input, that is, all clock signals can be provided by the input clock of CLKI. For the bus clock BCLK of SSD1906, the required BCLK can be obtained for CLKI by configuring the CD[7:6] pins. Here, CF[7:6] is configured to 00, that is, BCLK=CLKI.

The memory clock MCLK is used to access the SRAM inside the SSD1906. The design of the SSD1906 fully considers power saving control. When the display controller is not working, the clock is automatically turned off. On the other hand, reducing the frequency of MCLK will increase the MCU clock delay, thereby reducing the performance of screen refresh. Therefore, in order to achieve the best balance between power saving and performance, the frequency configuration of MCLK must meet two points: a high enough memory access frequency to provide a faster refresh rate, and an acceptable value for the MCU delay. The MCLK clock is obtained from the BCLK by configuring the register REG[04h].

The pixel clock PCLK is used to control the LCD panel. The selection of PCLK must match the optimal frame rate of the LCD panel. The frame rate is calculated as

Frame rate = fPCLK/(HT)×(VT)

Where: fPCLK is the PCLK clock frequency, in Hz;

HT = ((REG[12h] bits 6-0) + 1) × 8Ts, which is the total horizontal period;

VT=（（REG[19h]bits 1-0,REG[18h]bits 7-0）+1）lines, which is the total vertical period.

The selection of pixel clock PCLK has great flexibility. First, the frame rate of LCD panel generally has an allowable range. Second, the pixel clock frequency can also be specified as a very small value, and then the frame rate can be reduced to an optimal value by adjusting the horizontal and vertical display periods. The clock source of the pixel clock can be MCLK or BCLK. Different PCLKs can be obtained by configuring register REG[05h].

4.2 Setting the virtual display mode

SSD1906 supports virtual display mode, which can be realized by setting the following registers. First, set the main window display start address registers REG[74h], REG[75h], and REG[76h] to specify the start address of the main window image in the display memory. Then, set the main window line address offset registers REG[78h] and REG[79h] to determine the horizontal pixel number of the virtual image. Of course, the set horizontal pixel number must be greater than the actual display pixel width of the LCD panel to achieve virtual display, otherwise it is a normal display mode. Figure 3 shows the relationship between the main window and the virtual display area.

4.3 Floating window settings

The floating window can be located anywhere within the virtual display area, and its positioning can be set through the floating window control register REG[7Ch] to REG[91h]. The color depth and display direction of the floating window are the same as those of the main window. In this solution, the normal direction mode display is adopted, that is, the display rotation is prohibited. Figure 4 shows the relationship between the floating window and the main window in this solution, as well as the setting of the positioning register.

4.4 Hardware cursor settings

SSD1906 supports displaying two hardware cursors in the main window. The two cursors can be located anywhere in the main window, and the specific positioning is controlled by the cursor mode register REG[C0h] to REG[111h]. The hardware cursor only supports 4/8/16bpp display mode.

The color depth and display direction of the cursor are consistent with the main window. The positioning of the cursor and the corresponding control register settings in this solution are shown in Figure 5.

Here we only introduce the configuration of some main registers in SSD1906. For other register settings, please refer to related materials.

Conclusion

SSD1906 is a small-to-medium-scale graphic display controller, especially suitable for LCD display of industrial control, portable equipment and other daily consumer products. In the AT91RM9200 embedded system, the advantages of SSD1906, such as small size, low power consumption, low cost and multiple display functions, are fully utilized, and it can be well applied in the fields of industrial control and vehicle-mounted GPS.

Keywords：SSD1906 AT91RM9200 Reference address：Interface technology between SSD1906 display controller and AT91RM9200

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