Based on ARM high-speed flash memory MCU to meet a wide range of embedded needs

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Due to the use of the ARM7TDMI-S core, the LPC2000 series MCU has an operating frequency of 60MHz, which has stronger functional scalability than other 8-bit products. At the same time, it uses the on-chip memory plus module to achieve "zero wait access" high-speed flash memory function, improving the efficiency of instruction execution.

In addition, LPC2000 has a wide range of peripheral interfaces, including UART, SPI, I2C, CAN, ADC, PWM, RTC, etc. LPC2000 series MCUs are widely used in a wide range of fields, from network communications, motor control, to automobiles and consumer electronics.

Embedded systems are user-oriented, product-oriented, and application-oriented. They are the product of combining advanced computer technology, semiconductor technology, electronic technology, and specific applications in various industries. Therefore, they are a highly intensive and constantly innovative knowledge integration system. As an embedded system, it must be able to tailor the software and hardware according to the needs of the application and streamline the system to meet the various requirements of the application system in terms of function, reliability, cost, volume, etc.

Embedded processors are the core part of embedded system hardware. Philips has launched more than ten high-performance, low-power LPC2000 series microcontrollers based on ARM7 to meet the growing needs of the embedded market.

This series of new microcontrollers LPC2114/2124/2119/2129/2194, LPC2210/2212/2214, LPC2290 /2292/2294 provide enhanced communication functions and on-chip code protection mechanisms based on high performance and low power consumption. Due to the built-in wide range of serial communication interfaces, they are also very suitable for communication gateways, protocol converters, embedded soft modems, etc. The 6-channel PWM can be used for complex motor control applications. In short, the application areas of Philips ARM embedded microcontrollers include industrial control, communications, security systems, medical instruments, aerospace, automobiles and consumer electronics, covering low-end to high-end embedded product applications.

ARM7 micro-core architecture

Taking LPC2214 as an example, its structure block diagram is as follows:

Figure 1, LPC2214 block diagram

The CPU of LPC2214 is a 16/32-bit ARM7TDMI-S processor that supports real-time simulation and tracing. This processor is mainly used for applications with demanding power consumption and cost requirements. The use of three-stage pipeline technology enables efficient execution of instructions. In addition to supporting the standard 32-bit ARM instruction set, the ARM7TDMI-S processor also supports the 16-bit THUMB instruction set. The THUMB code is only 65% ​​of the size of the ARM code, but its performance is equivalent to 160% of the performance of the same ARM processor connected to a 16-bit memory system.

The on-chip system clock is generated by an external oscillator through a phase-locked loop multiplication, with a maximum operating frequency of up to 60MHZ. The on-chip memory controller is interfaced with the CPU through a separate local bus. The purpose of this is to avoid the uncertainty of bus arbitration, bus acquisition delays and wait cycles on the bus, thereby achieving higher real-time performance.

The interrupt controller and external bus controller are interfaced with the CPU via the AMBA high performance bus (AHB). The external bus controller supports 8/16/32-bit external memory.

The LPC2214 chip peripherals are connected to the AHB bus through the VPB bus and the AHB to VPB bridge. It also has multiple serial interfaces, including 2 16C550 industrial standard UARTs, a high-speed I2C interface (400 kHz) and 2 SPI interfaces. It also has 8-channel 10-bit A/D converters (0~3V measurement range), with conversion time as low as 2.44uS; 2 32-bit timers (with 4 capture and 4 comparison channels); PWM unit (6 outputs); real-time clock and watchdog, 112 general I/O ports (can withstand 5V voltage); 2 low-power modes: idle and power-down.

On-chip high-speed flash memory

The on-chip flash memory of the LPC2000 series is designed for embedded applications. It uses a 0.18-micron process, dual-transistor cells and a durable write/erase mechanism, which can achieve 10,000 write/erase cycles, an optimized 128-bit wide array, and zero-wait access, allowing programs to run at full speed. It also provides an on-chip program protection mechanism to prevent code from being copied.

Figure 2, Memory Acceleration Module

The LPC2000 series microcontrollers can achieve high-speed flash memory with zero wait access, mainly due to the on-chip memory acceleration module. Figure 2 is a block diagram of the memory acceleration module. The 128-bit wide flash array interfaces with the processor through a separate local bus, providing four 32-bit instructions to the ARM core per cycle. This allows the MCU to execute instructions directly from the flash memory without going through a wait state, thereby eliminating the waiting time when reading from the general flash memory. In order to solve the waiting time caused by the change of instruction sequence and the different processing of instructions and data, the module implements the joint work of three functional blocks: pre-fetch buffer, data bypass to avoid data read/write disrupting the address sequence, and jump tracking buffer, and uses two groups of 128-bit wide memories for parallel access to eliminate delays.

The role of the memory acceleration module depends on the size of the system clock. The access time of the on-chip flash memory of the LPC2000 series is 50nS. For applications with a system clock of no more than 20MHZ, the contents of the flash memory can be read out within 1 cycle, and there is no need to use the memory acceleration module. The higher the clock frequency, the greater the impact on system performance when the code in the flash memory is executed directly. At this time, enabling the memory acceleration module can achieve nearly 4 times the speed acceleration, truly realizing zero-wait high-speed flash memory. Since the LPC2000 can execute instructions directly from the flash memory, there is no need to transfer the code to the SRAM during the boot process. This not only saves the time-consuming and energy-consuming system startup steps, but also saves expensive SRAM.

Programming of the on-chip flash memory can be accomplished in several ways: through the built-in serial JTAG interface, through the serial port for in-system programming (ISP), or through in-application programming (IAP). [page]

Rich external bus interface

The LPC22XX series products provide an external memory interface, which includes 24 address lines A0~A23, 32 data lines D0~D31 and related bus enable lines; the data line width can be selected to be 8 bits, 16 bits or 32 bits. Figure 3 is a schematic diagram of the external memory connection with 32 data line width and 8/16/32-bit data line width:

Figure 3, 32-line data width external memory interface

LPC22XX provides four independent and simultaneously configurable memory groups, each with 16MB of address space, and can be properly connected and accessed with SRAM, Pseudo-SRAM, FLASH, EPROM, BURST ROM or other I/O DEVICEs.

If you choose a product with on-chip flash memory, you can choose to start the program from the on-chip flash memory or from an external memory. The LPC22XX series also provides programmable wait cycles and idle cycles, allowing up to 32 wait cycles and 16 idle cycles to be inserted.

Vectored Interrupt Controller

LPC2000 series

The vector interrupt controller can support up to 32 interrupt requests, which can be programmed into 3 categories as needed: FIQ, vector IRQ and non-vector IRQ. Fast interrupt request (FIQ) requires the highest priority. Vector IRQ has medium priority. This level can be assigned 16 of the 32 requests. Non-vector IRQ has the lowest priority. This programmable allocation mechanism means that the interrupt priorities of different peripherals can be dynamically assigned and adjusted. For any vector interrupt, once a request is issued, the CPU can read the VIC and jump to the entry address of the corresponding interrupt service routine in one cycle, which minimizes the interrupt delay.

Reference Design: Tax Control Cash Register

The tax control cash register is an electronic cash register with a tax calculation function. It is not only a powerful assistant for business management, but also a law enforcement representative for tax personnel to collect sales data in stores. It is equipped with a tax calculation memory that automatically records but cannot be changed or erased. It records daily business data and tax payable, and is the proof of paying taxes to the tax authorities.

China passed the "National Standard for Tax Control Cash Registers" on October 1, 2003. The implementation of this standard has spawned a huge tax control machine market.

The tax control cash register consists of the following parts: Chinese display system; Chinese printing system; dedicated tax control processing system; peripheral device driver; power supply; chassis with physical security guarantee.

The tax control mechanism consists of an issuance, management, declaration, maintenance, and operation system based on IC cards. The records of the taxpayer's sales of goods in the tax control cash register and the relevant time and other information can be retained in the machine for 5 to 10 years and cannot be modified or deleted. The relevant data is read out by the tax department using a special IC card for audit.

Here is a minimum system reference design with LPC2214 as the main control unit. The system is mainly composed of the main control MCU module, clock module, power module, monitoring module, IC card reading and writing module, tax control memory, status indication circuit, interface circuit, etc. The hardware structure is shown in the figure:

Figure 4, Hardware block diagram of a tax control cash register using LPC2214

The embedded microcontroller uses Philips LPC2214, which makes full and reasonable use of its on-chip real-time clock, external memory interface, UART and other peripheral interfaces. The on-chip flash memory is used as the storage space for user programs, and its high-speed zero-wait feature ensures the real-time operation of the system. Its on-chip program protection mechanism prevents the code from being arbitrarily changed and copied. The design structure of the entire system is simple and has great competitive advantages.

The software design of the tax control cash register adopts a modular concept. The embedded controller uses an RTOS operating system based on the μC/OS kernel. The development of its user program is roughly divided into the following parts: main program, self-diagnosis module, IC card reading and writing module, UART communication module, invoicing module, LCD display, buttons and other human-machine interface modules.