Parallel Active Power Filter Controller Based on DSP ARM

In recent years, with the widespread application of power electronic equipment and nonlinear and impact equipment, the harmonics generated in the power grid have caused serious pollution to the power grid system. Therefore, eliminating harmonic pollution in the power grid has become an important topic in the study of power quality. The commonly used parallel passive filters have poor filtering effects and are sensitive to power grid parameters. The components are bulky. In severe cases, they may cause series-parallel resonance accidents and other defects. The active power filter (APF) technology using modern power electronics technology, digital signal processing (DSP) technology and advanced control theory can dynamically and real-time compensate for power grid harmonics. It is currently the most effective and most promising way to solve the problem of harmonic pollution.

Traditional parallel APF control methods are mostly based on calculation and measurement methods such as instantaneous reactive power theory and adaptive theory. First, the harmonic components in the load current are calculated, and then the compensation current and DC side capacitor voltage are controlled according to the calculated harmonic current values. This method requires more complex mathematical operations, which affects the response speed of the device. Current distortion is prone to occur when the load changes.

For the three-phase system, an APF control algorithm based on DC side capacitor voltage control is adopted. Starting from the perspective of instantaneous active and reactive power transmission in the system, the active power input to the APF from the power grid is adjusted as the goal, and the input current is directly controlled, eliminating the cumbersome process of detecting active and reactive current components, making the process of detecting harmonics simple. A fully digital parallel APF controller based on DSP and ARM is designed.

2 Control strategy

2.1 DC link capacitor voltage control algorithm

The control algorithm is used to inject appropriate energy into the capacitor on the power side to compensate for the loss caused by the disconnection of the power electronic device and maintain the stability of the DC side capacitor voltage H. The integral of the loss power in the actual compensation device within a cycle is not zero, which will cause the change of the cycle value of u, which reflects the transfer of active power on both sides of the inverter.

The algorithm controls the active current input from the power supply on the AC side to compensate for the loss of the switching device. The integral of the compensation power PA on the AC side within one cycle is:

The energy change in one cycle, that is, the amount of electricity stored on the DC capacitor, can be expressed as:

The compensation goal is to make the two equations equal by combining equations (1) and (2). With r as a unit, the size of the equivalent compensation current on the AC side can be calculated. Figure 1 shows the single-cycle control block diagram of the DC side voltage designed based on this. After periodic sampling and correcting the sampled voltage comparison value through the proportional integral link, the amplitude k of the loss current can be obtained. Make the loss current in phase with the system voltage to ensure that it is an equivalent active current: control the transmission of active power to ensure stability near a certain value. [page]

As can be seen from Figure 1, the regulation of uout forms a negative feedback, which satisfies the requirement that out is always near a certain fixed value.

2.2 Harmonic compensation

For a stable harmonic source, the harmonics of the load can be compensated by superimposing the harmonic detection link in the control loop. You can choose to compensate for full compensation or specific harmonics. At the same time, add a limiting link in the harmonic detection link to offset the impact of sudden changes in load and protect the circuit. The extraction of harmonic current can be calculated according to the FFI method:

2.3 Overall control block diagram

Figure 2 shows the overall control block diagram. The target current output includes two parts: control and harmonic current detection. A hysteresis comparison is performed with the actual compensation current output by the compensator. A three-phase PWM signal is output to control the converter.

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3 Active Power Filter Control System Design

The designed APF control system adopts DSP+ARM dual-core structure. DSP completes sampling control, A/D conversion, voltage regulation and command current calculation, and ARM realizes peripheral expansion function.

It uses a 32-bit fixed-point digital signal processor TMS320F2808 that was recently launched. It has a rich set of on-chip peripherals:

The two event manager modules each contain two 16-bit timers. They complete the PWM signal generation, signal indication and fault protection functions; the 12-bit ADC with a minimum conversion time of 160 ns completes data acquisition; the CAN, SCI and SPI communication interfaces complete the fast communication function. Its maximum main frequency is 100 MHz and the single instruction cycle is 10 ns. It can well meet the control requirements of the APF control system.

The LPC2364 ARM chip is used. It is based on an ARMTTDMI.STM CPU microcontroller that supports real-time simulation and embedded tracing. It is powerful and cost-effective. It supports 10/100 Ethernet, full-speed USB2.0 and CAN2.0B. It has up to 512 kB of FLASH and 58 kB of SRAM. It can easily realize the human-machine interface composed of LCD display and keyboard. And the communication function with the host computer. The control system block diagram is shown in Figure 3.

The three-phase voltage signal in the power grid, the DC side voltage signal, the load current signal and the APF output signal are sent to the DSP for conversion after signal conditioning. The built-in A/D module of the DSP has a 12-bit resolution and a pipeline structure. According to the sampled data, the TMS320F2808 calculates the actual output compensation current of the APF and performs a hysteresis comparison. The output three-phase PWM signal controls the converter. At the same time, the hardware dead zone control method is formed by using logic devices, and the corresponding logic hardware drive protection is designed in conjunction with the IGBT module to improve the reliability of the system.

CAN communication is adopted between DSP and ARM, and the communication speed can reach 1 Mb/s, which can well meet the requirements of high-speed data transmission.

ARM calls the MCU data through the CAN bus and expands the FLASH chip to store data. The chip uses 16 MB FLASH in I/O mode. 8 blocks can be expanded on the board. The output of the 38 decoder is used as the selection signal. It is mainly used to store LCD display data: the ARM chip uses a standard SPI interface. Interact with the display board: with a standard 232/485 interface. It is used for host computer communication and expansion of communication port functions. Such as printers, etc.

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The system program consists of the main program and the timer overflow interrupt program.

The main program is responsible for DSP system initialization and variable initialization. It completes the sampling of the three-phase system and executes the control algorithm in Figure 4a, including the digital phase-locked loop, voltage PI regulation and id calculation; the interrupt program shown in Figure 4b is responsible for the three-phase hysteresis comparison control.

4 Simulation and Experiment

Under the condition of asymmetrical harmonic load, the power simulation software EMTP was used for simulation (waveform omitted). From the simulation results, it can be seen that the three-phase system current before compensation has an asymmetrical and non-sinusoidal waveform and contains a large number of harmonics; after compensation, ih, ik are symmetrical and in phase with the system voltage.

Figure 5 shows the measured waveform after compensation using the set APF. Comparing the two figures, the harmonic content is significantly reduced after compensation, and the APF harmonic compensation effect is obvious.

5 Conclusion

A shunt active power filter based on DSP-ARM full digital control is designed for three-phase system. A DC side voltage control method based on the principle of energy conservation is adopted, which can fully compensate for harmonics. And this control strategy is still effective for unbalanced three-phase system. After compensating the asymmetric harmonic source, the three-phase current can be kept symmetrical. The simulation and actual test results show the correctness of this control strategy. It can make the system have good harmonic suppression characteristics and response speed.