Single chip microcomputer application realizes unmanned monitoring and analysis solution of remote computer room equipment on the network

1 Ethernet controller

The Ethernet controller of Taiwan Realtek is a controller that complies with the IEEE802.3 Ethernet standard. There are RTL8019, RTL8029 and RTL8139 series. Among them, RTL8019 is ISA bus, which is easier to interface with 8-bit MCU. RTL8029 and RTL8139 are PCI bus, which cannot directly interface with 8-bit MCU, and need a PCI interface for conversion. Considering that RTL8029 is easier to buy in the market, the RTL8029 Ethernet controller is used as the network interface.

RTL8029 already contains the entire network interface layer protocol (PHY layer and MAC layer protocol), so it is relatively simple to use. Users do not need to consider link control issues, but only need to consider how the microcontroller reads TCP/IP protocol data from RTL8029.

PCI bus signals have 3.3V standard and 5V standard, and there are many signal lines, but not all PCI devices use all PCI interface signals. In fact, only the ones they need are used. The RTL8029AS Ethernet controller follows the 5V standard and only uses the following parts of the PCI bus signals:

AD[31:0]——Data signal multiplexing bus.

FRAME - frame period signal, driven by the current master device, indicating the start and duration of an access.

IRDY——Master device ready signal.

TRDY——Slave device ready signal.

C/BE——Bus command and byte enable multiplexed signal. The address period is the bus command, and the data period is the byte enable.

IDSEL - Initialization device select signal. Used as chip select during parameter configuration read and write transfers. For situations where there is only one PCI device, it can always be connected to a high level.

RST——reset signal.

CLK——System clock signal, frequency range DC~33MHz. The above signals are all valid on the rising edge of CLK.

INTA - interrupt request signal, which can be used to send an interrupt to the main controller when the RTL8029 data is ready.

DEVSEL - Device selection signal, indicating that the device driving it has become the currently accessed device. Since RTL8029 is a single PCI device in the single-chip microcomputer system, this signal can be ignored.

2 PCI interface design

Among the interface signals of the Ethernet controller, except for the address data bus which is bidirectional, the TRDY signal is generated by the Ethernet controller and its direction is from the Ethernet controller to the PCI interface; the remaining signals are generated by the interface part and their direction is from the PCI interface to the Ethernet controller.

The idea of ​​interface design is: the PCI interface can be regarded as the external memory of the microcontroller. The microcontroller reads and writes the PCI interface with the timing of reading and writing the external memory, and then the PCI interface converts the read and write operation timing into PCI timing to operate the Ethernet controller.

The signals used by the microcontroller when performing external memory operations include PO port, P2 port, ALE, RD and WR signals. Among them, P0 port is address (low 8 bits)/data multiplexing, P2 port is high 8-bit address signal; ALE is address latch signal, when high level, the value of P0 port is latched to the low 8-bit data line; RD and WR are read and write valid signals, low level is valid. Therefore, the PCI interface actually plays a role in converting the read and write timing of 8-bit microcontroller to 32-bit PCI read and write timing. The principle block diagram is shown in Figure 1, and the access timing is shown in Figure 2.

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In Figure 2, configuration access and I/O read and write access to the PCI device can be completed. As long as these two types of access are available, the microcontroller can fully implement the operation of RTL8029. The IDSEL signal is only used in configuration access and is not used in I/O access.

The first clock edge after FRAME is valid is the beginning of the address period. At this time, the address is transmitted on the AD bus and the command is transmitted on the C/BE bus. After IRDY is valid, it is the data period. At this time, data is transmitted on the AD bus and byte enable is transmitted on the C/BE bus. However, data transmission is performed on the clock edge when IRDY and TRDY are both valid. Byte enable indicates which data byte is valid in the data on the 32-bit data line at this time.

The process of reading configuration: first send the address, command (command value is 1010B) and byte enable, and then read the contents in the configuration space.

The process of writing configuration: first send the address, send the command (the command value is 101lB) and byte enable, and then send the configuration data.

The process of reading I/O: first send the address, command (command value is 0010B) and byte enable, and then read the contents in the I/O space.

The process of writing I/O: first send the address, send the command (the command value is 001lB) and byte enable, and then send the data.

In I/O access, the two bits AD[1:O] have special requirements and need to be coordinated with C/BE[3:0].

When C/BEO is valid, AD[1:0] must be 00, and when C/BE3 is valid, AD[1:0] must be 11. In a specific access, every time a device address is decoded and selected, it is necessary to check whether the byte enable signal is consistent with AD[1:0]. If the two are inconsistent, the entire access will not be completed. Therefore, when writing microcontroller software, it is necessary to refer to the content of this part in the PCI bus protocol in order to correctly operate the Ethernet controller.

Within one clock cycle after the address of the bus command/byte enable (C/BE) register is valid, the FRAME signal should be valid, indicating the start of the address period. The C/BE[3:0] bus is the bus command. The address period can last only one cycle, and then immediately enter the data period. In the single-chip microcomputer system, it is not necessary to consider supporting complex PCI data bursts. After entering the data period, the FRAME signal should be immediately pulled back to a high level. At this time, the C/BE[3:0] bus is byte enable. Therefore, the FRAME signal can be generated using the address signal of the bus command/byte enable register.

The IRDY signal is valid only during the data period, so IRDY can also be generated by the address signal of the bus command/byte enable register or by the FRAME signal.

The IDSEL signal is only related to configuration access, so it can be generated by the command word of the bus command. During I/O access, the highest bit 3 of the command word is 0; during configuration access, the highest bit 3 of the command word is 1. Therefore, this bit can be used to generate the IDSEL signal.

In addition, as mentioned above, the PCI interface can be accessed as an external memory, so the 8-bit data must be converted into 32-bit data. The following registers need to be designed in the PCI interface:

Register 0, corresponding to AD[7:0] of the 32-bit data/address bus, is used for writing;

Register 1, corresponding to AD[15:8] of the 32-bit data/address bus, is used for writing;

Register 2, corresponding to AD[23:16] of the 32-bit data/address bus, is used for writing;

Register 3, corresponding to AD[31:24] of the 32-bit data/address bus, is used to write:

Register 4, corresponding to AD[7:O] of the 32-bit data/address bus, is used for reading;

Register 5, corresponding to .AD[1 5:8] of the 32-bit data/address bus, is used for reading;

Register 6, corresponding to AD[23:16] of the 32-bit data/address bus, is used for reading;

Register 7, corresponding to AD[31:24] of the 32-bit data/address bus, for reading;

Bus command/byte enable register, corresponding to C/BE[3:0];

Reset register, used to reset the hardware of RTL8029AS.

Based on the above analysis, the PCI interface principle block diagram is obtained, as shown in Figure 3.

3 VHDL Implementation of Interface

The VHDL code of the PCI interface can be found on our website: www.dpj.com.cn.

The above code is compiled and synthesized under Qaartus II, occupying 149 macrocell resources, and can be completed using the CPLD device MAx7l60.

4 Conclusion

The design method described in this paper has been successfully applied to the remote control of the radio monitoring system. Through the 5l single-chip microcomputer system connected to Ethernet, unmanned monitoring of remote equipment in the computer room can be realized on the network.