Cumulative error analysis and clock frequency optimization for UART communication in MSP430FR2311

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Cumulative error analysis and clock frequency optimization for UART communication in MSP430FR2311 [Copy link]

In UART communication design, engineers will first select the appropriate baud rate according to system needs, and then select the appropriate clock source frequency to minimize the cumulative error when UART transmits data and the bit error rate of the data. This article takes MSP430FR2311 as an example to conduct a detailed analysis and calculation of the cumulative error of the transmitter and the cumulative error of the receiver during UART data transmission. According to the calculation results, engineers can optimize the clock source frequency to improve the reliability of the UART data transmission system.

In the article in Appendix 1, the analysis and calculation of the UART module register configuration of MSP430FR2311 are introduced in detail, which will not be repeated here. BRCLK is the clock source frequency, and BITCLK is the baud rate. When BRCLK is an integer multiple of BITCLK, that is, BRCLK/BITCLK=N, since each data bit contains N BRCLKs, which is exactly the same as the ideal value, there is no time error for each data bit, so there is no cumulative error during data transmission. However, in most cases, BRCLK is not an integer multiple of BITCLK. Since the duration of each data bit is an integer multiple of BRCLK during data transmission, there is a time error in each data bit, so there is a cumulative error during data transmission.

The following is a 4-part analysis and calculation of the cumulative error: the cumulative error of the transmitter at low-frequency baud rate, the cumulative error of the transmitter at high-frequency baud rate, the cumulative error of the receiver at low-frequency baud rate, and the cumulative error of the receiver at high-frequency baud rate.

Cumulative error of the transmitter at low-frequency baud rate

With the clock source frequency BRCLK 32768Hz and the baud rate BITCLK Taking 2400 Hz as an example, 32768/2400=13.6533, so UCOS16=0, UCBRx=13, UCBRSx=0xB6.

As shown in Figure 1, at the end of sending each data bit, there is an error between the actual sending duration and the ideal sending duration.

For the Start bit, the ideal duration is 13.65BRCLK, the actual duration is 14BRCLK, and the error duration is 13.65BRCLK-14BRCLK=-0.35BRCLK.

For the LSB bit, the ideal duration is 13.65BRCLK, the actual duration is 13BRCLK, the error duration is 13.65BRCLK-13BRCLK=0.65BRCLK, and the cumulative error duration is -0.35BRCLK+0.65BRCLK=0.30BRCLK.

For Bit1, the ideal duration is 13.65BRCLK, the actual duration is 14BRCLK, the error duration is 13.65BRCLK-14BRCLK=-0.35BRCLK, and the cumulative error duration is 0.30BRCLK-0.35BRCLK=-0.05BRCLK.

The errors and cumulative errors of subsequent bits are similar.

Figure 1 Schematic diagram of cumulative error at the transmitter of low-frequency baud rate

The following is the derivation of the formula for cumulative error at the transmitter of low-frequency baud rate.

t_bits_ideal_TX is the ideal cumulative data duration at the transmitter.

t_bits_ideal_TX = (i+1)/BITCLK (1) t_bit_period_TX is the actual bit duration of each data at the transmitter. The number of BRCLKs for each data is equal to the sum of the UCBRx value and the corresponding modulation value UCBRSx.m of UCBRSx. t_bit_period_TX = (UCBRx +UCBRSx.m)/BRCLK (2)t_bits_TX is the cumulative data duration actually sent by the transmitter.t_bits_TX[0] = t_bit_period_TX[0] (3)t_bits_TX = t_bits_TX[i-1] + t_bit_period_TX, where i≠0 (4)

Define Error_TX as the difference between the actual accumulated data duration and the ideal accumulated data duration, relative to the percentage of the ideal data bit duration, the unit is %

Error_TX=(t_bits_ideal_TX-t_bits_TX)*BITCLK*100 (5)

Table 1 shows the calculation results of Error_TX with the data in the routine.

From Table 1, we can see that the maximum positive Error_TX is 3.91% and the minimum negative Error_TX is -3.12%.

Table 1 Error_TX

Accumulated error of transmitter at high-frequency baud rate

With clock source frequency BRCLK 4000000Hz, baud rate BITCLK Taking 57600 as an example, 4000000/57600=69.4444, so UCOS16=1, UCBRx=4, UCBRFx=5, UCBRSx=0x55.

As shown in Figure 2, at the end of the transmission of each data bit, there is an error between the actual transmission duration and the ideal transmission duration.

For the Start bit, the ideal duration is 69.44BRCLK, the actual duration is 69BRCLK, and the error duration is 69.44BRCLK-69BRCLK=0.44BRCLK.

For LSB For Bit1, the ideal duration is 69.44BRCLK, the actual duration is 69BRCLK, the error duration is 69.44BRCLK-70BRCLK=-0.56BRCLK, and the cumulative error duration is 0.44BRCLK-0.56BRCLK=-0.12BRCLK.

For Bit1, the ideal duration is 69.44BRCLK, the actual duration is 69BRCLK, the error duration is 69.44BRCLK-69BRCLK=0.44BRCLK, and the cumulative error duration is -0.12BRCLK+0.44BRCLK=0.32BRCLK.

The errors and accumulated errors of subsequent bits are similar.

[align=ce Figure 2 Schematic diagram of cumulative error of transmitter at high-frequency baud rate

The following is the derivation of the formula for cumulative error of transmitter at high-frequency baud rate.

t_bits_ideal_TX is the ideal cumulative data duration of the transmitter.

t_bits_ideal_TX = (i+1)/BITCLK (6)

t_bit_period_TX is the actual bit duration of each data at the transmitter. The number of BRCLKs for each data is equal to the sum of 16*UCBRx+UCBRFx value and the corresponding modulation value UCBRSx.m of UCBRSx.

t_bit_period_TX = (16*UCBRx+UCBRFx +UCBRSx.m)/BRCLK (7)t_bits_TX is the cumulative data duration actually sent by the transmitter.t_bits_TX[0] = t_bit_period_TX[0] (8)t_bits_TX = t_bits_TX[i-1] + t_bit_period_TX, where i≠0 (9)

Define Error_TX as the difference between the actual accumulated data duration and the ideal accumulated data duration, relative to the percentage of the ideal data bit duration, the unit is %

Error_TX=(t_bits_ideal_TX- T_bits_TX)*BITCLK*100 (10)

Table 2 shows the calculation results of Error_TX with the data in the routine.

From Table 2, we can see that the maximum positive Error_TX is 0.64% and the minimum negative Error_TX is -0.80%.

Table 2 Error_TX

Accumulated error at the receiving end of low-frequency baud rate

The MSP430FR2311 User's Guide points out that the error at the receiving end consists of two parts: one is the error from the start edge of the start bit at the transmitter to the edge being recognized by the receiver, and the other is the deviation between the actual recognition time and the ideal recognition time of each data bit. As shown in Figure 3. Figure 3 Two types of errors at the receiving end

The first error is represented by Tsync, Tsync = ±0.5BRCLK.

For the second error, since the receiver ideally samples and identifies at the position of half the data bit duration, the error calculation is based on this moment, unlike the transmitter, which uses the position at the end of the ideal data bit duration as a reference.

The calculation formulas are given in the MSP430FR2311 User's Guide, but these formulas contain too many elements to be easily understood. This article uses a simplified way to understand and calculate, and can obtain the same cumulative error results. Figure 4 is a schematic diagram of the Majority Vote of MSP430FR2311. It can be seen from the figure that Majority Vote samples data at three edge positions, and the sampling center position is INT(N/2)+m, where N=INT(BRCLK/BITCLK), m is the UCBRSx.m value corresponding to the data bit in UCBRSx. The ideal data bit sampling center position is 0.5/BITCLK.

Figure 4 Majority Vote diagram

So for the i-th data bit starting from the Start bit, its sampling center position time is Tsync, the sum of the actual total duration of the first i-1 data bits and the sampling center position duration of the data bit is then compared with the ideal i-th data bit sampling center position time, and the cumulative error of the i-th data bit can be obtained.

Take the clock source frequency BRCLK 32768Hz and the baud rate BITCLK 2400Hz as an example, 32768/2400=13.6533, so UCOS16=0, UCBRx=13, UCBRSx=0xB6. The ideal data bit sampling center position is 13.6533/2=6.8267BRCLK.

As shown in Figures 5 and 6, at each data bit sampling center position, there is an error between the actual cumulative sampling time and the ideal cumulative sampling time.

When Tsync=0.5BRCLK is considered, as shown in Figure 5.

For the Start bit, the ideal data bit cumulative sampling center position time is 6.83BRCLK, the actual data bit cumulative sampling center position time is 7.5BRCLK, and the error is 6.83BRCLK-7.5BRCLK=-0.67BRCLK.

For LSB bit, the ideal data bit cumulative sampling center position time is 20.48BRCLK, the actual data bit cumulative sampling center position time is 20.5BRCLK, and the error is 20.48BRCLK-20.5BRCLK=-0.02BRCLK.

For Bit1, the ideal data bit cumulative sampling center position time is 34.13BRCLK, the actual data bit cumulative sampling center position time is 34.5BRCLK, and the error is 34.13BRCLK-34.5BRCLK=-0.37BRCLK.

The accumulated errors of the subsequent bits are similar.

When Tsync=-0.5BRCLK is considered, it is shown in Figure 6.

The analysis method is the same as Figure 5 and will not be repeated here.

[img]https://e2echina.ti.Figure 5 Schematic diagram of the cumulative error at the receiving end of low-frequency baud rate, Tsync = 0.5BRCLK

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Figure 6 Schematic diagram of the cumulative error at the receiving end of low-frequency baud rate, Tsync=-0.5BRCLK

The following is the derivation of the formula for the cumulative error at the receiving end of low-frequency baud rate. t_bits_ideal_RX is the time when the ideal data bit accumulation sampling center is at the receiving end. t_bits_ideal_RX = (i+0.5)/BITCLK (11)t_bit_period_RX is the actual data bit sampling center position time at the receiving end. The number of BRCLKs at the sampling center position of each data bit is equal to the sum of INT(0.5UCBRx) and the corresponding modulation value UCBRSx.m of UCBRSx.t_bit_period_RX = [INT(0.5*UCBRx) +UCBRSx.m]/BRCLK (12)t_bits_before_RX is the actual accumulated data duration of all i-1 data bits before the current data bit.t_bits_before_RX[0] = 0t_bits_before_RX[i-1] + (UCBRx[i-1] + UCBRSx.m[i-1])/BRCLK, where i≠0 (13)

Where t_bits_before_RX[i-1] is the actual accumulated data duration of all i-2 data bits, (UCBRx[i-1] + UCBRSx.m[i-1])/BRCLK is the actual data duration of the i-1th data bit. t_bits_RX is the time of the actual data bit cumulative sampling center position at the receiving end. t_bits_TX = Tsync + t_bit_period_RX + t_bits_before_RX (14) Error_TX is defined as the percentage of the error between the actual data bit cumulative sampling center position at the receiving end and the ideal data bit cumulative sampling center position at the receiving end as a percentage of the ideal data bit duration, in units of % Error_TX = ( t_bits_ideal_TX - T_bits_TX)*BITCLK*100 (15)

Table 3 shows the Error_TX data brought into the routine.

From Table 3, we can see that the maximum positive Error_TX is 8.84% and the minimum negative Error_TX is -5.52%.

Table 3 Error_TX

Accumulated error at the receiving end of high-frequency baud rate

Take the clock source frequency BRCLK 4000000Hz and the baud rate BITCLK 57600 as an example, 4000000/57600=69.4444, so UCOS16=1, UCBRx=4, UCBRFx=5, UCBRSx=0x55. The ideal data bit sampling center position is 69.4444/2=34.7222BRCLK. As shown in Figures 7 and 8, at the time of each data bit cumulative sampling center position, there is an error between the actual sampling time and the ideal sampling time.

When Tsync=0.5BRCLK is considered, as shown in Figure 7.

For the Start bit, the ideal data bit cumulative sampling center position time is 34.72BRCLK, the actual data bit cumulative sampling center position time is 34.5BRCLK, and the error is 34.72BRCLK-34.5BRCLK=0.22BRCLK.

For LSB bit, the ideal data bit cumulative sampling center position is 104.16BRCLK, the actual data bit cumulative sampling center position is 104.5BRCLK, and the error is 104.16BRCLK-104.5BRCLK=-0.34BRCLK.

For Bit1, the ideal data bit cumulative sampling center position is 173.60, the actual data bit cumulative sampling center position is 173.5BRCLK, and the error is 173.60BRCLK-173.5BRCLK=0.10BRCLK.

The accumulated errors of the subsequent bits are similar.

When Tsync=-0.5BRCLK is considered, it is shown in Figure 8.

The analysis method is the same as Figure 7 and will not be repeated here.

Figure 7 Schematic diagram of the cumulative error at the receiving end of high-frequency baud rate, Tsync = 0.5BRCLK

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Figure 8 Schematic diagram of the cumulative error at the receiving end of high-frequency baud rate, Tsync=-0.5BRCLK

The following is the derivation of the formula for the cumulative error at the receiving end of high-frequency baud rate. t_bits_ideal_RX is the time when the ideal data bit accumulation sampling center is at the receiving end. t_bits_ideal_RX = (i+0.5)/BITCLK (16)t_bit_period_RX is the actual data bit sampling center position time at the receiving end. The number of BRCLKs at the sampling center position of each data bit is equal to the sum of INT[0.5*(16*UCBRx+UCBRFx)] and the corresponding modulation value UCBRSx.m of UCBRSx.t_bit_period_RX = [INT(0.5*(16*UCBRx+UCBRFx)) +UCBRSx.m]/BRCLK (17)t_bits_before_RX is the actual accumulated data duration of all i-1 data bits before the current data bit.t_bits_before_RX[0] = 0t_bits_before_RX[0] = 0t_bits_before_RX = t_bits_before_RX[i-1] + (16*UCBRx+UCBRFx + UCBRSx.m)/BRCLK, where i≠0 (18)

Where t_bits_before_RX[i-1] is the actual accumulated data duration of all i-2 data bits, (16*UCBRx+UCBRFx + UCBRSx.m)/BRCLK is the actual data duration of the i-1th data bit. t_bits_RX is the time of the actual data bit cumulative sampling center position at the receiving end. t_bits_TX = Tsync + t_bit_period_RX + t_bits_before_RX (19) Error_TX is defined as the percentage of the error between the actual data bit cumulative sampling center position at the receiving end and the ideal data bit cumulative sampling center position at the receiving end as a percentage of the ideal data bit duration, in units of % Error_TX = ( t_bits_ideal_TX - T_bits_TX)*BITCLK*100 (20)

Table 4 shows the Error_TX data brought into the routine.

From Table 4, we can see that the maximum positive Error_TX is 1.76% and the minimum negative Error_TX is -1.12%.

Table 4 Error_TX

Clock source frequency optimization

The clock source frequency optimization needs to consider two factors:

• Try to reduce the cumulative error of the transmitter and the cumulative error of the receiver
• For the Majority Vote architecture, too high a clock source frequency will reduce the detection window of Majority Vote and reduce the performance of Majority Vote

Take the baud rate of 9600Hz as an example, Error_TX and Error_RX are shown in Table 5. According to the clock source optimization principle, 1000000 Hz is selected.

Table 5 Error_TX and Error_RX

[td=106 ]

BRCLK

BITCLK

Error_TX+ (%)

[p =21, null, left]Error_TX- (%)

Error_RX+ (%)

Error_RX- (%)

32768

9600

16.02

-17.19

37.30

-23.24

1000000

9600

0.64

-0.48

1.04

-1.04

8000000

9600

0.04

-0.08

0.14

-0.10