A clock system design based on phase-locked loop

Figure 1: Phase-locked loop application in clock generation.

Phase-locked loops are widely used in clock system design, including phase synchronization and clock multiplication. Usually, when the chip operating frequency is higher than a certain frequency, it is necessary to eliminate the phase difference between the on-chip clock and the off-chip clock caused by the on-chip clock drive. The PLL embedded in the chip can eliminate this clock delay. In addition, many chip control chain logics require a clock with a duty cycle of 50%, so a clock source with a duty cycle of 2 times is required. The PLL integrated in the chip can synthesize the external clock into this clock source.

System-integrated PLLs can be triggered internally, which is faster and more accurate than external triggers, and can effectively avoid some problems related to signal integrity. Another notable feature of system-integrated PLLs is that by adjusting the parameters in the clock tree buffer located in the PLL feedback loop, the PLL can generate core clocks with different multiples of the reference input clock frequency. This adjustment ensures fast synchronization and effective data transmission between the chip and the external interface circuit.

In the design of high-performance processor clock systems, a phase-locked loop is usually required to generate on-chip clocks. This paper takes a 200MHz clock system design as an example to introduce a clock system design based on a phase-locked loop, where the input reference frequency is 25MHz, the phase noise is -100dBc/Hz@100kHz, the voltage-controlled oscillator gain is 380MHz/V, and the operating voltage is 5V. Simulation and test results show that the design can meet the system requirements.

Loop Structure

The clock generation structure based on the phase-locked loop is shown in Figure 1: the external 25MHz reference clock signal or bus clock (BusCLK) first enters a receiving buffer, and before entering the phase frequency detector (PFD), it passes through a divider with a frequency division coefficient of M1 _{, and obtains φi} in Figure 1 , and then compares it with the internal feedback signal φo from _{the divider M6} in the PFD to obtain the error signal φe _, which will be used as the input of the charge pump and the filter network to control the voltage-controlled oscillator (VCO). VSPACE=12 HSPACE=12 ALT="Figure 2: Phase detector structure.">

The output of the VCO is first divided by M3 _and then buffered to generate the system's main clock PClk. At the same time, the main clock passes through the H-tree clock distribution network before entering the divider M6 _, and finally returns to the phase detector, thus forming a complete feedback loop. From a balance perspective, the two inputs of the PFD must be consistent in frequency and phase, so the ratio of the chip core clock and the input bus clock fpclk _/ fbus _must be equal to M6 _/ M1 _. By changing the values ​​of M6 _and M1 _, integer or fractional multiples of the input clock frequency can be obtained. Since the chip requires that the clock cannot drift, the output clock duty cycle and the system's phase adjustment capability must be insensitive to changes in the environment and process parameters. The output of the VCO can also be switched to the divider M5 _, and the output can be used as the clock of the secondary cache (L2). Similarly, fvco ₌ M3 _× fpclk ₌ M5 _× fL2CLK _, and the output frequency of the secondary cache can also be adjusted by M3 _and M1 _to obtain an ideal value.

Loop composition analysis

The entire loop includes modules such as phase detector, filter, voltage-controlled oscillator, frequency divider, common-mode suppression and lock detection. The following introduces the structure of the main modules:

1. Phase detector

The output signal generated by the digital frequency and phase detector can express the relative advance or lag information of frequency and phase, and then sent to the charge pump. After the reset signal arrives, each rising edge of θ _{i triggers the "UP" signal until a rising edge of θ o} arrives, thus ending the set state of UP and entering the system reset state. Similarly, if the rising edge of θ _o arrives before θ _i , "DOWN" is set until a rising edge of θ _i arrives, and then enters the reset state. Unless the two input phases and frequencies are very close, that is, entering the so-called "phase detection dead zone", the width of the general pulse is proportional to the phase difference between the two inputs. The structure of the phase detector is shown in Figure 2.

2. Voltage Controlled Oscillator

The voltage controlled oscillator is a key component in the phase-locked loop. There are many structures in practical applications. Figure 3 is a commonly used structure. The D delay unit is the key component of the entire loop, and the selection unit M is responsible for selecting different data channels.

As can be seen from Figure 3, the entire voltage-controlled oscillator is based on a ring oscillator with an internal delay unit. Compared with current-injection and current-modulation voltage-controlled oscillators, this type of differential ring oscillator is widely used in chip clock generation circuits. At the same time, the voltage-controlled oscillator with an embedded delay unit has a relatively low VCO gain, so it is very suitable for differential control and circuit implementation on the signal path. Experiments show that the "jitter" of the oscillator with a low-gain embedded delay unit is significantly smaller than that of the high-gain ring, because noise is easily decoupled in the low-gain structure. The operating frequency of the embedded delay link of the oscillator is generally limited. To ensure the monotonicity of the loop, the ratio of the upper and lower limits must generally be less than 2:1, but it can also be effectively improved by selecting an appropriate divider ratio coefficient or adding programming capabilities to the VCO signal path.

The frequency range of the voltage-controlled oscillator depends on the longest and shortest delays on the path. As shown in Figure 3, the outer dotted box represents the route of the maximum frequency f _h , which goes through 3 delay units D and a selection unit M. The inner dotted box represents the route of the minimum frequency f _l , and its path includes 6 delay units D and a selection unit M. The selection of different units will also affect the gain of the voltage-controlled oscillator and the loop center frequency. The frequency range can be determined individually by selecting different delay paths using a multi-way switch, thereby flexibly adjusting the frequency range of the VCO, far exceeding the frequency range determined by the VCO gain. [page]

The delay unit and selection unit in Figure 3 can be based on a PMOS source-coupled differential amplifier with an NMOS load, which can also achieve voltage-controlled swing adjustment, mainly by adjusting the voltage and changing the effective load line. The high impedance state of the current source increases the power supply noise suppression of the source-coupled component. At the same time, the N-well also effectively isolates a large amount of noise on the P-type substrate, increasing the system noise suppression performance.

Simulation Results

The designed circuit is simulated using SpectreRF in Cadence, using 0.6μm, 3V/5V, double poly, double aluminum CMOS process parameters. VCO is a key module in the phase-locked loop. PSS and PNoise analysis of VCO can obtain its phase noise graph, as shown in Figure 4. The phase noise is approximately -110dBc/Hz at 100kHz. Figure 5 is the gain curve of VCO, the gain is about 380MHz/V, and it has good linearity.

Design Summary

Since the phase-locked loop contains analog circuits, noise interference is also a problem that needs to be overcome in the design. The power supply noise generated by the flip of large digital circuits affects the operation of the analog circuits in the phase-locked loop. The output clock cycle will change due to the influence of power supply noise or other interference sources (such as thermal noise of MOS tubes), which is usually called output "jitter". Clock jitter will directly affect the highest operating frequency of the integrated circuit because it will reduce the available clock cycle. As the available clock cycle decreases, the digital circuits on the critical path cannot get enough time to process data in one cycle, which directly leads to the so-called "critical path error". In addition, when there is high-power chip interference or mixed digital and analog circuits share a common substrate, the impact of power supply noise is more obvious.

_{The frequency deviation Δf out} and phase deviation Δθ _out caused by the noise source with frequency f _m at the output can be expressed as:

Δθ _out =Δf _out /f _m

The performance of high-frequency noise and low-frequency noise varies greatly due to their different generation mechanisms, so the suppression methods adopted in different applications are also different. Low-frequency noise generally includes power supply ripple, random thermal noise of resistors and transistors, random flicker noise of transistors, etc. High-frequency noise mainly comes from the high-speed flipping of digital circuits and the fast switching of chip control components. In chip clock design, this type of noise is dominant. Because the frequency of high-frequency noise is relatively high, the phase shift Δθ _out generated is relatively small. Generally, high-frequency noise is described by periodic "jitter".

The classic phase-locked loop contains analog circuits and is therefore very sensitive to noise. For on-chip integrated phase-locked loops, the following measures are generally used to eliminate noise:

1. Surround the entire phase-locked loop with power and ground wires. The ground coil can keep the substrate potential around the phase-locked loop stable. The constant substrate potential can suppress noise, and most of the noise introduced by the input and output units and other logic circuits is introduced through substrate coupling.

2. Separate the power line of the phase-locked loop from the power lines of other chip systems. Because instantaneous large currents often appear in the logic circuit part or the interface circuit part, the potential of the main power supply changes continuously. The constant change of power supply voltage will affect the noise suppression function of the phase-locked loop. Therefore, when designing the power supply and ground of the phase-locked loop, the main power supply part should be separated from the phase-locked loop power supply part, and both should be given with separate pins.

3. Place the input pin of the PLL next to the PLL to protect it from power supply fluctuations and other interference.