Application of SoC Technology in FC Chip Design

Introduction

Fibre Channel (FC) is a high-performance bidirectional point-to-point serial data channel. The standard for Fibre Channel was developed by the T11 Standards Committee (a technical committee under the National Information Technology Standardization Committee of the United States). It is a computer communication protocol designed to meet the growing requirements for high-performance information transmission. FC combines the advantages of IO channels and networks. It supports both the bandwidth and reliability required by IO channels and the flexibility and connectivity of network technology, making it possible to run today's popular channel standards and network protocols on the same physical interface. At present, FC has been used as a major networking standard for the future unified network of avionics. This paper discusses a solution for designing FC protocol chips using system-on-chip (SOC) technology, analyzes the characteristics of SOC design methods and their differences from traditional embedded system design methods, and lays the foundation for promoting the use of SOC technology in the design of avionics systems in the future. Introduction to FC

Working Principle

The physical media supported by Fibre Channel include optical fiber, twisted pair, coaxial cable, etc., which are collectively referred to as optical fiber in this paper. Physically, FC can be viewed as a connection of multiple communication points called N ports. These N ports can be connected through a switching network and form an arbitration loop through a hub, or they can be connected through a point-to-point link. As shown in Figure 1, the FC protocol can be divided into a series of functional layers, each of which is briefly described below.

Figure 1 FC hierarchy diagram

FC-0 layer
FC-0 defines the physical characteristics of the interface and the medium, and specifies the optoelectronic parameters of the transceiver and various physical media. Depending on the implementation device, FC can have different data transmission rates: 133Mbit/s, 266Mbit/s, 530Mbit/s, 1.0625Gbit/s, etc.

FC-1 layer
FC-1 defines the encoding and decoding and transmission protocol, which uses a DC balanced 8b/10b code. An 8-bit byte is encoded as 10 bits for transmission and then decoded at the receiving end. A portion of unused code points with special characteristics are used to form special characters to form an ordered set of signaling and frame descriptions.

FC-2 layer
FC-2 layer is the signal transmission protocol layer. It specifies the rules for data transmission, provides a transmission mechanism for data blocks from one port to the next, and defines the functions and devices that can be used by FC-4, of which FC-4 can only use a subset. This layer describes the following concepts:
(1) Nodes and N-ports and their corresponding identifiers;
(2) Communication model;
(3) Topology;
(4) Service class;
(5) General switching network model;
(6) FC-2 building blocks and architecture;
(7) Frame format;
(8) Sequence;
(9) Switching.

FC-3 layer
The FC-3 layer provides common services required for some advanced features, such as:
(1) Classification: Using several N-ports in parallel to increase bandwidth so that a single message
can be transmitted over multiple connections. (2) Query group: Enable more than one port to respond to the same alias address. This service improves efficiency by reducing the chance of contacting busy N-ports.
(3) Multicast: Sending a transmission to multiple destination ports, including sending to all N-ports on a switching network (broadcast), or only to certain N-ports on the switching network. [page]

FC-4 layer
The FC-4 layer is the highest layer of the FC protocol, which specifies the mapping of upper layer protocols to the FC protocol. The currently mapped protocols are: Small Computer System Interface (SCSI), Intelligent Peripheral Interface 3 (IPI-3), High Performance Parallel Interface (HIPPI), INTERNET Protocol (IP), IEEE802.2, Single Byte Command Code Set Mapping (SBCCS). In addition, FC-AE also describes an upper layer protocol mapping based on 1553B.

The physical model of FC-PH
The FC channel is physically composed of at least 2 nodes. Each node can be composed of multiple N ports, and each N port provides the functions of FC-0, FC-1, and FC-2. FC-3 is optional, and it provides common services for multiple N ports and FC-4. The composition of the FC node is shown in Figure 2.

Figure 2 Composition of FC nodes

Each port consists of a pair of optical fibers, one for input and one for output. This pair of optical fibers and transceivers transmitting in opposite directions form an FC link to complete data transmission. The frame

format
of the FC-2 layer is shown in Figure 3.

The frame start delimiter SOF is an ordered set of 4 8b characters, with different code words depending on the type of frame; frame header, 24 8b characters, see Table 1 for details; data field, 0–2112 8b characters; CRC, 4 8b characters, it checks the frame header part and the data field part, and its coding polynomial is X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1; the frame end delimiter EOF is an ordered set of 4 8b characters, with different code words depending on the type of frame.


Design overview of FC protocol chip

Functional overview
The function of FC chip is to implement FC-PH in Figure 1, that is, the protocols of FC-2, FC-1, and FC-0 layers; each FC chip supports 2 N ports, which can form an FC node as shown in Figure 2; the supported data transmission rate is 1.0625Gbits/s.

Design considerations based on SoC
There are similarities between SoC-based chip design and embedded module board design, but SoC design cannot be simply understood as the miniaturization of embedded module boards. Their main differences are as follows:
(1) The design of embedded module boards is implemented using existing CPU chips and peripheral chips, while SoC design is implemented by CPU cores and various functional module cores.
(2) As can be seen from the above, the design of embedded module boards is carried out within a set rule framework. These rules are the user manuals of various chips, while SoC design can design rules according to design requirements and then design various functional module cores to meet functional requirements and optimize resource utilization.
(3) Design of embedded module board. Due to the limitation of CPU chip pins, most peripheral chips are hung on an external bus of CPU, which inevitably leads to bus contention. In principle, there is no limit on the number of buses that can work in parallel inside the chip in SoC design. We should make full use of this feature, reasonably determine the architecture, and avoid bus contention.
(4) Design of embedded module board. Its software and hardware design have fixed patterns. However, SoC design must first determine the intersection of software and hardware according to design requirements and determine the rules of software and hardware collaboration to achieve the purpose of optimizing resource utilization. [page]

First, we need to determine the intersection of software and hardware. The intersection of software and hardware is placed on the "sequence" of FC-2 layer. Because the "sequence" is responsible for receiving or sending the entire block of data, when the length of the data block exceeds the data length shown in Figure 3, it must be divided into several related data frames for transmission. The relevance of the data frame is shown in the frame header as shown in Table 1. Only the sequence count field SEQ_CNT changes. Therefore, the software will be responsible for providing part of the information and data of the frame header, and the hardware will be responsible for data framing and subsequent work. Secondly, when designing the chip architecture, the parallel bus inside the chip should be fully utilized. Finally, to facilitate the testing of this chip, the upper layer interface ULP should first consider using the PCI bus to implement the FC network card based on the PCI interface. According to the actual use requirements in the future, the ULP will be designed on demand.

Chip structure
According to the discussion in Section 3.2, the structural block diagram of the FC protocol chip is shown in Figure 4. The FC protocol chip uses the PCI interface for the upper layer interface (ULP), which is implemented by the PCI-TARGET core built into the chip.

Figure 4 FC protocol chip structure diagram

The dotted box in Figure 4 constitutes the FC N-port, and there are two N-ports in the entire chip. Each FC-N port consists of two layers: "FC transceiver channel" and "FC frame transceiver controller". The "FC transceiver channel" cooperates with the optoelectronic interface module to realize the data frame transceiver function in the FC-0 layer, FC-1 layer and FC-2 layer. This layer provides the upper layer interface with an on-chip FIFO channel for data frame transceiver. The "FC frame transceiver controller" implements the data frame packaging, unpacking and error detection of the FC-2 layer. In addition, the sequence and exchange protocol of the FC-2 layer is implemented through the software module embedded in the chip; at the same time, a ULP interface is provided. The FC channel, frame transceiver controller, CPU core and ULP interface are discussed separately below.

Design of FC transceiver channel module

Functional overview
This module mainly completes the transmission and reception of FC-2 layer frames, including: completing the connection between SERDES (serial-to-parallel conversion module) and the optoelectronic interface, completing the 8b/10b encoding and decoding of the FC-1 layer, the CRC check of the FC-2 layer frame level and the decoding of the FC ordered set code; at the same time, the built-in memory is used to form a FIFO buffer for data exchange with the FC chip back-end module.

Composition structure
This module is divided into "FC transmission channel" and "FC reception channel", as shown in Figure 5. A variety of self-loop test paths are provided between the transmission and reception channels (not marked in the figure).
The "FC transmission channel" is mainly composed of the following units:
(1) Parallel-to-serial conversion unit;
(2) Transmit clock phase-locked loop;
(3) 8b/10b encoding unit;
(4) CRC check generation unit;
(5) TX-FIFO transmission control unit;
(6) TX-FIFO data input buffer unit;
(7) Self-loop control unit.

The "FC receiving channel" is mainly composed of the following units:
(1) serial-to-parallel conversion unit;
(2) receiving clock phase-locked loop;
(3) clock recovery unit;
(4) synchronization detection unit;
(5) ordered set decoding unit;
(6) 8b/10b decoding unit;
(7) CRC check unit;
(8) RX-FIFO send control unit;
(9) RX-FIFO data output buffer unit;
(10) self-loop control unit.

Figure 5 FC channel structure diagram [page]

Definition of data transceiver buffer
The definition of data buffer TX-FIFO and RX-FIFO is shown in Table 2: The transmit buffer is 33 bits, the lower 32 bits are the data to be transmitted, and the 32nd bit is used to indicate whether the current codeword is an ordered set code. The receive buffer is 36 bits, the lower 32 bits are the received data, and the upper part stores the CRC check result of the FC-2 frame, the decoding check of the 8b/10b code and other information.


5.1 Functional Overview
There are two "FC frame transceiver modules and their data buffers" in the FC chip, which implement the frame packaging and unpacking in the FC-2 layer protocol. It is the intersection of the hardware and software of the entire system and the core of the entire system. The key lies in formulating relevant design rules.

5.2 Rules for using data buffer
According to the principle of parallel operation of multiple buses, four independent data buffers are set, using dual-port RAM to exchange data between the CPU and the frame transceiver. The rules for using the transmit and receive data buffer are as follows:
(1) Transmit buffer TXBUF. According to the FC-2 frame format shown in Figure 3, this buffer is used to store the frame header and valid data. The first 24 bytes are the frame header area for storing the frame header, followed by the valid data area. When sending, the module TXF-CTL takes the frame header information from the frame header area and sends it. According to the values ​​of the send start address (TXOFFSET) and the send number (TXCOUNT) in the register, it continuously takes data from TXBUF and sends it. Here, only one frame header area is set, considering that the frame header has relevance in the "sequence". At the same time, there is no switching of multiple areas in one frame header area, which simplifies the hardware implementation.
(2) Receive buffer RXBUF. This buffer adopts a circular queue method, and the module RXF-CTL writes data sequentially. The data storage order is shown in the FC-2 frame format in Figure 3. After completing the reception of one frame of data, the module RXF-CTL must indicate the receive start address (RXOFFSET) and the number of received (RXCOUNT) of the current frame in the RXBUF in the register. After the CPU reads the register RXCOUNT, the register is automatically cleared. The above usage rules are the key points of the entire system for SoC design.

Working process

Data transmission process Send:
(1) CMD_RESET. The module TXF-CTL is reset and enters the idle state.
(2) CMD_TEST: The CPU directly controls the data transmission, and the module TXF-CTL enters the idle state.
(3) CMD_START_TX1: In the idle state and when both CMD_TEST and CMD_START_TX2 are invalid, the module enters the state of sending data by frame, and the module TXF-CTL sends a SENDING signal. The module TXF-CTL first sends the ordered set code IDLE (K28.5D21.4D21.5D21.5) to the TX-FIFO of the FC transmission channel; sends the corresponding SOF according to the SOF pattern register; then takes the data from the frame header area of ​​TXBUF and sends it in sequence; later, if the data is taken from TXBUF, the corresponding data is taken from TXBUF according to the register sending start address (TXOFFSET) and the number of transmissions (TXCOUNT) to send; after sending the valid data, the corresponding EOF is sent according to the EOF pattern register; finally, an ordered set code IDLE (K28.5D21.4D21.5D21.5) is sent. After a frame of data is sent, the SENDING signal is cleared, CMD_START_TX1 is cleared, the interrupt signal INTTXi is sent, and then the idle state is returned. The sending process can only be interrupted by CMD_RESET.
(4) If the data comes from the ULP-FIFO, read the number of transmissions (TXCOUNT), take the data from the ULP-FIFO and send it. If the number of transmissions (TXCOUNT) is greater than the length specified by the FC-2 frame, it will be sent in multiple frames according to the length of 2112 bytes. After each frame is completed, the frame count value in the frame header is automatically modified, and the corresponding SOF and EOF delimiters are automatically selected; if the ULP-FIFO is empty during the transmission process, the transmission of this frame will be automatically terminated, and the timeout timer will be started to wait for the data in the ULP-FIFO. When the data specified by the number of transmissions (TXCOUNT) is sent, or the timeout is exceeded, the SENDING signal will be cleared, CMD_START_TX1 will be cleared, the interrupt signal INTTXi will be sent, and then the idle state will be returned. The transmission process can only be interrupted by CMD_RESET.
(5) CMD_START_TX2: In the idle state, when CMD_START_TX2 is valid, the module TXF-CTL
sends the ordered set code according to the definition of the ordered set code register and the ordered set code parameter register.

Data receiving process
There are two ways to receive data: directly controlled by the CPU; and received by RXF-CTL in FC-2 frame format. The CPU can send commands to the module RXF-CTL through the register of the FC-2 frame transceiver controller to control data transmission:
(1) CMD_RESET. The module TXF-CTL is reset and enters the idle state.
(2) CMD_TEST: The CPU directly controls the reception of data.
(3) CMD_START_RXi: In the idle state and when CMD_TEST is invalid, it enters the state of receiving data in frames. After receiving the ordered set code SOF from the RX-FIFO of FCSET-A, the module RXF-CTL sends a RECEIVE signal, indicating that the reception of 1 frame of data has begun. The module RXF-CTL writes the received data into the circular buffer RXBUF in sequence. After receiving any ordered set code, the reception of 1 frame of data is completed, and the RECEIVE signal is cleared. Update the register receiving start address (RXOFFSET) and the number of received data (RXCOUNT). If the received CRC code is invalid or the last ordered set code is not EOF, the reception error (RXERR) is set to '1', otherwise the INTRXi interrupt signal is issued, indicating that 1 frame of correct data has been received. Continue to receive the next frame of data. During the process of receiving 1 frame of data, only CMD_RESET can interrupt; if 1 frame of data has not yet been received, CMD_TEST can return it to the idle state. The CPU reads registers RXOFFSET, RXERR and RXCOUNT to know the address and number of the received data and whether the data frame is valid.

In addition, CMD_START_Rxi is also used to control the RX-FIFO controller in the FC receiving channel. CMD_START_Rx1 controls the FC receiving channel to receive data according to the FC-2 frame and store it in the RX-FIFO; CMD_START_Rx2 controls the FC receiving channel to receive all data (except continuous IDLE ordered set codes) and store them in the RXFIFO.

Configuration of built-in CPU and design of ULP

The built-in CPU completes the sequence and exchange protocol of the FC-2 layer through embedded software, and realizes the communication between ULP and the upper layer.

CPU peripheral configuration
The CPU peripherals and bus interface are defined as follows:
(1) Two RS232 serial ports.
(2) Watchdog timer: WATCHDOG-TIMER.
(3) Two timers for FC-2 layer communication: FCTIMER1 and FC-TIMER2.
(4) PIO for receiving interrupts from two FC-2 frame transceiver controllers: INTFRAME-PIO. Two PIOs for receiving ordered set decoding from RX-FIFO: ORDERSET-PIO1, ORDERSETPIO2. Two internal bus interfaces for operating two FC-2 frame transceiver controllers. The registers of the FC-2 frame transceiver controller can be defined according to the operation function requirements.

(5) Four independent internal bus interfaces for connecting the transceiver data buffers. (
6) Three independent memory bus interfaces: dual-port RAM, program memory and data memory.
(7) ULP-RXFIFO interface for exchanging data with ULP.
(8) ULP-PIO interface for handshaking with ULP.

ULP data channel
As shown in Figure 4, the FC chip provides two data channels for ULP: dual-port RAM and FIFO. Dual-port RAM channel: It can be divided into several partitions according to the needs of ULP, and ULP can access it through the PCI interface. The built-in CPU of the FC chip reads data from the dual-port RAM, puts it into TXBUF, and then starts the "frame transmission module" to package and send; when receiving data, the CPU reads data from RXBUF, stores it in the corresponding data partition of the dual-port RAM, and notifies the ULP to fetch data. This data channel is more effective for messages that need to be confirmed and retransmitted when errors occur.

FIFO channel: ULP writes data to ULP-TXFIFO through the PCI interface, and the CPU sets the "frame transmission module" to fetch data from ULP-TXFIFO. When the data is packaged, the "frame transmission module" fetches data from ULP-TXFIFO; when receiving data, the CPU reads data from RXBUF and stores it in ULP-RXFIFO. This data channel is more effective for messages with high real-time requirements such as video data.

Basic operation functions of FC chip embedded software

The embedded software of the FC chip must complete the functions of FC-2 layer switching, sequencing, frame transmission and reception, error control, and flow control. The basic operation functions they need to call are listed in Table 3. These basic operation functions are related to the hardware platform, and other functions performed on the platform will be independent of the hardware platform. This is conducive to the collaborative development of software and hardware and the isolation of errors. This is another important principle of SOC design.

Conclusion

At present, high-end FPGAs have embedded transceivers, phase-locked loops and a large amount of memory that adapt to high-speed transmission. The FC protocol chip discussed in this article can be used to implement prototypes on such FPGAs. Fiber Channel will be widely used in the future unified avionics network due to its high transmission speed and good compatibility. The FC protocol chip discussed in this article will lay a material foundation for this application. Taking the design of the FC protocol chip as an example, this article introduces the key points of thinking based on SoC design and the basic principles of SoC design, which will help promote the use of SoC technology in the design of avionics systems.