Analysis of SDRAM Timing Control in High-Speed ​​Embedded Video Systems

In the application of high-speed digital video system, the use of large-capacity memory to achieve data caching is an essential link. SDRAM is a kind of memory that is often used.

However, the timing jitter problem between the main chip and SDRAM hinders the mass production of products. In the actual application of digital TV receiver production, the differences in PCB board wiring, PCB materials and clock frequencies of different manufacturers, as well as the differences in SDRAM models and device consistency, will cause the jitter problem of access timing between the decoding main chip and SDRAM.

This paper uses the timing compensation mechanism provided by the SDRAM controller built into the C-NOVA digital TV MPEG-2 decoder chip AVIA9700 to design a convenient memory timing test software tool. With this tool, development and test personnel can quickly diagnose and solve SDRAM timing problems in the design and production of digital TV receivers using AVIA9700 as a decoder.

Digital TV system

SDRAM timing control

AVIA9700 integrates an SDRAM controller, which provides a complete set of SDRAM interfaces. The control lines, address lines and data lines in the interface between AVIA9700 and SDRAM are synchronized on the MCLK clock. FIG. 1 is a typical connection diagram of a 32-bit data line formed by combining two 16-bit SDRAMs.

Figure 1 Typical connection diagram between SDRAM and AVIA9700

SDRAM control lines

The correct read and write timing conditions

for the AVIA9700 decoder chip to access SDRAM are shown in Figure 2.

Figure 2 AVIA9700 access SDRAM timing diagram

To correctly access SDRAM, setup time and hold time are critical. Setup time is before the trigger sampling, during which the data must remain valid, otherwise setup violation will occur; hold time is after the demodulator starts sampling, during which the data must remain valid, otherwise hold violation will occur. Therefore, to correctly read and write SDRAM timing conditions, the following two formulas need to be met:
SDRAM_Setup_time_min < T_cycle-control_signal_valid_max-control_signal_Delay_max+ clock_delay_min (1)
SDRAM_Hold_time_min < control_signal_valid_min + control_signal_delay_min- clock_delay_m_ax (2)

Here, T_cycle is the SDRAM clock cycle, Control signal valid is the control signal from the rising edge of the clock to the valid output, and delay is the delay caused by wiring.

For low-frequency design, the influence of wire interconnection and board layer is very small and can be ignored. When the frequency exceeds 50MHz or the signal rise time Tr is less than 6 times the transmission line delay, the interconnection relationship must be taken into account based on the transmission line theory, and the electrical parameters of the PCB material must also be considered when evaluating the system performance. Since the AVIA9700 output clock signal MCLK operates between 108MHz and 148.5MHz, the SDRAM timing problem caused by wiring delay must be considered during design. [page]

AVIA9700 SDRAM

timing control mechanism

In order to compensate for the wiring delay and meet the requirements of formula (1) and formula (2), the built-in SDRAM controller of AVIA9700 provides two delay compensation parameters: SDRAM_CLK_IN and SDRAM_CLK_OUT. Both parameters are 8-bit integers that can provide different clock delay combinations to solve SDRAM timing problems in various complex digital TV receiver systems.

Through embedded application software, developers can adjust the parameters of SDRAM_CLK_IN to control the clock delay of reading data. Similarly, the setting of SDRAM_CLK_OUT can also change the delay of the output clock. By setting SDRAM_CLK_OUT (OutTapSel=X) to change the output MCLK clock phase and compensate for various wiring delays, the SDRAM timing problem of high-speed digital TV systems can be solved.

In practical applications, different machine manufacturers use SDRAM from different manufacturers, PCB wiring will also change greatly due to machine structure reasons, and the inconsistency of clock operating frequency and selected equipment will cause the parameters in formulas (1) and (2) to change. The combination of these factors often makes the wiring delay problem complicated.

AVIA9700 SDRAM

timing diagnostic software and test results

In order to facilitate developers to quickly solve problems, this paper uses the clock delay compensation mechanism provided by the built-in SDRAM controller of AVIA9700 to design a diagnostic tool.

Based on the AVIA9700 digital TV receiver, since the PCB, components, and system frequency have been finalized, the electrical characteristics that affect the wiring delay have been solidified. By changing the combination of SDRAM_CLK_IN and SDRAM_CLK_OUT, designers can test the SDRAM access error rate under different combinations and make a statistical chart based on the error rate statistics, as shown in Figure 3. The vertical axis in the figure is SDRAM_CLK_IN. Since the register is 8 bits, the coordinate value range is selected between 0 and 255 (28); the horizontal axis is SDRAM_CLK_OUT, and the value range is also between 0 and 255. For the register setting corresponding to a certain point in this range, the diagnostic software must automatically repeat the read and write operations 10,000 times. Designers can use the final generated graph to quickly and accurately select the values ​​of SDRAM_CLK_IN and SDRAM_CLK_OUT, and solidify them in the final production version of the software.

Figure 3 SDRAM timing test statistics

Here, the principle for selecting the compensation parameters is that the combined value needs to be in the center of the error-free area of ​​the test image and be greater than 25 from the boundary.

Conclusion

Through experiments, it is found that in the design of high-speed digital systems, compensating wiring delays through SDRAM controllers can effectively solve SDRAM timing problems. ■

References
1. Howard Honson, Martin Graham. High-Speed ​​Digital Design [M]. Electronic Industry Press. 2004
2. AVIA9700 datasheet C-NOVA, Inc. 2004
3. AVIA9700 programming guide C-Nova, Inc. 2004