Design and implementation of embedded FPU microinstruction control module

1 Introduction

The design and research of high-performance, high-precision microprocessors (MPUs) suitable for national defense and civilian needs has become extremely important and urgent. In order to process a large amount of real data and consider calculation accuracy and real-time performance, it is necessary to separate a part of the MPU for floating-point operations. For example, the current high-end digital signal processing chips (DSPs) all contain an FPU, so the development of high-performance floating-point unit IP is of great significance [1].

The concept and principle of microprogramming was first proposed by MV Wilks, a professor at the Department of Mathematics at Cambridge University in 1951 [2]. However, in the following 15 years, the development of microprogramming technology was restricted by the problem of control memory. With the development of LSI and VLSI control memory, microprogramming has begun to play an important role in microcomputers.

The performance of microprogram controller is one of the key factors to improve processing speed. The research on microprogram controller in this paper is based on the design of 32-bit FPU of Microelectronics Center of Harbin Institute of Technology (Weihai). It adopts the method of microinstruction control and completes the design of related modules at gate level. The results after layout and routing show that the design is small in scale and high in speed, which is very suitable for embedded applications.

2 Structure and design of microprogram controller

The generation of control signals in a microprocessor is generally achieved by two methods: microprogram and state machine. Microprogram belongs to firmware. The microinstructions output by the microprogram controller are used to control the entire FPU operation [3]. A microprogram generally consists of two major parts: operation control and sequence control. The control part is used to manage and direct the operation of the FPU [4]. The sequence control part of the microprogram is used to determine the address of the next microinstruction. The microprogram controller has its own advantages, such as regularity, flexibility, and maintainability. The structure of the microprogram controller of this design is shown in Figure 1.

Figure 2 Microinstruction selection control [page]

The microprogram controller mainly consists of three parts: a micro-address generation module for generating the next microinstruction, a memory for storing microinstructions (this is a ROM) and a control bus for commanding the FPU to work. The first two parts are the main ones, which are introduced below:

2.1 Introduction to micro-address generation module

The main purpose of the micro-address generation module is to generate the address of the next micro-instruction. The address line width is 8 bits, and the next micro-address is generated by the following (as shown in Figure 2):

1. The ExcMiptr signal is used to select the entry address of the exception operation and control corresponding to various exceptions (including inaccurate result exception, overflow, underflow and invalid exception) generated during the execution of an FPU instruction.

2. The nextMiptr signal is used to select the address of the next microinstruction generated during the normal execution of an FPU instruction.

3. The RomEntry signal is used to select the entry address of different instructions according to the FPU instructions. This design has different control entry addresses for single-precision and double-precision addition, subtraction, multiplication, division, and multiplication-addition instructions.

4.RomMiptr signal is the default docking address of the micro address, that is, the default address output when reset and FPU is idle

5. The feedback signal is used to select the address for the jump microinstruction, such as the jump control for multiplication and addition and multiplication and subtraction instructions in this design.

As mentioned above, the control of these address signals all comes from the control bits of the microinstructions. The control of whether to generate a branch is shown in Figure 3.

Figure 3 Microinstruction branch control signal generation diagram

2.2 Microinstruction Storage Module

The storage module of this microinstruction controller has 8-bit address input and 64-bit data output for managing and controlling the entire FPU. The 64-bit microinstruction is the control signal used to control the entire system. Its function is similar to that of a state machine. In this design, the possible states in the data processing process are detected through the microinstruction [15:11], and then the state transition is performed according to different states. The main ones are listed in Table 1 below:

Table 1 Microinstruction control bits

3. Module implementation and verification

The microprogram module adopts a top-down design method. All components are designed as IP (Intellectual Property) according to the modular concept, and the interface signal timing between modules is clear. At the same time, the logic control in the module is designed at the gate level to optimize the performance of the design. Using Synopsys' Design Compiler as a synthesis tool, using SMIC 0.18 micron process, the synthesized result clock frequency is 266MHz.

The system uses the hardware description language Verilog as the working language and uses Modelsim SE6.2 to complete the entire simulation process. The simulation results fully comply with the requirements of the IEEE754 standard [5] and can achieve single-precision and double-precision control. After the simulation is completed and verified by FPGA, it lays a solid foundation for future tape-out. [page]

Generally speaking, design verification methods include two categories: simulation methods and formal methods. This design adopts the simulation method. The simulation verification environment is shown in Figure 3. Using the assertion-based verification method, it is mainly divided into three parts: the stimulus part, the module to be tested, and the verification comparison module.

Figure 3 Simulation verification environment