LED display hardware design based on single chip microcomputer

Since the 1990s, with the continuous improvement of the design and manufacturing level of LED display technology, LED digital screens have gradually been widely used in production and life. With its unique display medium, LED digital screens have shown advantages in the fields of large-area, all-weather, high-brightness and ultra-high-brightness display screens. In the more than ten years of development of LED display technology, new devices and new technologies have been continuously adopted, manufacturing costs have gradually decreased, and production division of labor has been continuously refined. However, while being widely used, several defects of LED display technology have also been exposed. In general, the technology is not yet mature, and the standards have not yet been fully established. There are many aspects that deserve further research and improvement.

With the rapid development of large-scale integrated circuits, the computing and control capabilities of microprocessors have greatly increased. Single-chip computers have assumed intelligent tasks in many industrial and civilian systems. Compared with the rapidly developing computing speed, their port expansion capabilities are much inferior (limited number and difficult to expand). Therefore, a lot of energy has to be invested in saving ports during the research and development process. At present, in order to solve the port expansion problem in China, software processing can be used, which increases the difficulty of software writing, or a dedicated chip for port expansion can be used. These two methods will increase the software cost or the complexity of the hardware circuit, which is not conducive to the development of some small systems. The STC12C5A60S2 microcontroller has a variety of serial transmission modes, which solves this contradiction to a certain extent.

LED digital screens are widely used. They can not only display text, but also various graphics, charts, and even various animation effects. They are a powerful tool for advertising and news dissemination.

This paper uses STC12C5A60S2 microcontroller, interface NAND flash memory and host PC to realize the control of 16×128 dot matrix LED digital screen.

1. Chip selection

1.1 Screen

Since the screen is a commercial product, the system chip is preferably selected to match the screen. The screen has its own power supply, which can directly convert the energy of the battery into a 5 V DC power supply, and this power supply is also output to the system board through the interface cable of the screen. Therefore, the system can directly use this power supply without having to prepare its own power supply circuit.

1.2 Microcontroller

Taking into account the screen and system requirements, the single-clock/machine cycle (1T) microcontroller STC12C5A60S2 produced by China Hongjing Technology was selected.

STC12C5A60S2 is a new generation of high-speed 8051 microcontroller. Its instruction code is fully compatible with the traditional 8051, but it is 8 to 12 times faster. It integrates the MAX810 dedicated reset circuit internally, and its operating voltage range is 3.5 V to 5.5 V, which meets the required voltage. Since it is a single-cycle 8051 (the traditional 8051 is 12 cycles), you can choose an 11.059 2 MHz crystal oscillator that is easier to obtain an accurate baud rate without worrying about the reduction of operating speed.

STC12C5A60S2 has 60 KB user application space, 256 B RAM and 1024 B XRAM. It can meet the needs of program code and buffer definition. There is also a flash memory area independent of the program storage space, which can be used as EEPROM in application programming.

STC12C5A60S2 has dual UART and ISP serial ports, and the serial port resources are sufficient for system use. In addition, through the software provided by Macrocrystalline Technology, program download can be easily achieved using UART. STC12C5A60S2 has 36 general I/O ports, most of which can be bit-controlled and have strong push-pull output capabilities, which are sufficient for system use.

STC12C5A60S2 has four 16-bit timers and an independent baud rate generator, and two PCA modules, which can obtain rich timer resources. STC12C5A60S2 has a PDIP-40 package chip, which is easy to quickly enter the experiment.

1.3 Flash memory

Because the capacity of the Chinese character library of 16 × 16 dot matrix is ​​about 250 KB, and the addressing space of MCS51 is only 64 KB. For ordinary memory chips with an interface capacity greater than 64 KB, bus expansion must be performed, and the method of latching the address twice is used for reading and writing, which requires complex circuits and takes up a long access time. Similarly, the pin structure of NOR flash memory is similar to that of EPROM, with the same interface complexity and very high cost. To realize a simple interface between the microcontroller and the character library chip (without expansion), only a serial structure memory or a command, address and data multiplexing bus structure memory can be selected.

Most serial memory is EEPROM, which does not have a large capacity and is not suitable for font library chips. Therefore, only NAND flash memory with command, address and data multiplexing bus is used as font library storage chip.

The capacity required for the font library is not large, but it is best to be powered by 5 V, and the programming cache requires a smaller chip. The K9F4008W produced by SAMSUNG is a 512 KB NAND flash memory with only 8 IO ports and a wide operating voltage range (3 V~5.5 V). It is compatible with 3 V and 5 V hardware systems, and only requires a 32 B buffer during frame programming, which is just suitable as a chip for font library storage.

Therefore, the electrically erasable feature of the flash memory chip is very suitable for occasions where the character library needs to be replaced. Therefore, this chip is an ideal Chinese character library memory.

2 Circuit Design

The schematic diagram of the circuit designed according to the overall structure of the system is shown in Figure 1.

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3 Overall design

3.1 Screen interface module

The screen interface includes the screen interface header file, screen buffer definition, screen interface initialization, refresh timer interrupt service program and SPI interrupt service program.

The header file screen.h of the screen interface should make the screen buffer visible to other applications and provide a screen initialization function. The specific definition is as follows:

#ifndef _SCREEN_H_

#define _SCREEN_H_

#include "incboard.h"

extern u8 xdata SCR_BUF[16][16];

void screen_init(void);

#endif

This exposes the structure of the screen buffer to the application, but the application does not have to worry about the specific screen refresh operations.

The implementation of the specific screen interface is concentrated in a file screen.c. The details are as follows:

First the screen buffer definition:

u8 xdata SCR_BUF[16][16]_at_0x0000;//~0x00ff 256Bytes The following is the definition of the current display row and output column variables, which are static variables and are not visible to the application.

static u8 data row,col;

Then comes the screen initialization, including the initialization of refresh timer 0, the initialization of SPI, the initialization of the latch bLatch signal, the initial clearing of the screen buffer, and the initialization code of the priority and enable bits of the timer and SPI interrupts.

The interrupt service routines of SPI and timer 0 are the key to the screen interface.

The interrupt service routine of timer 0 first performs scan line increment modulo operation and outputs the scan line. Then, it takes out the first byte of the corresponding line in the screen buffer according to the scan line and sends it to the SPI port. At the same time, the column increments.

void display_ONe_screen(void)interrupt 1 using 3{

row = (++row)&0x0f;

P0 = (P0 & 0xf0) | ((~row) & 0xf);

col = 0;SPDAT = ~SCR_BUF[row][col++];

}

For a screen driver written in this way, the application only needs to write the data to be displayed into the screen buffer after initializing the screen, without having to worry about the details of the screen display.

3.2 UART Interface

The UART interface is responsible for sending and receiving data with the host computer. Although sending can be done synchronously, receiving must be done asynchronously. Therefore, the core of the UART interface should still be an interrupt service program.

The header file uart.h of the UART interface hides the information of the receiving buffer. The functions that users can call are only initialization, sending and receiving.

#ifndef _UART_H_

#define _UART_H_

void uart_init(void);

void uart_put_c(u8 ch);

u8 uart_get_c(u8 *);

#endif

The UART interface implementation first defines a receive buffer FIFO, as well as the read subscript uart_rd and write subscript uart_wr for the FIFO. They are static variables visible in the file:

static u8 xdata uart_buf[64];

static u8 uart_rd,uart_wr;

bit fSend

UART initialization includes FIFO initialization and UART format, baud rate, and interrupt initialization. The code is omitted.

The ISR of UART is mainly used for receiving, unconditionally loading data into FIFO, and adjusting the write pointer.

static void uart_isr(void)interrupt 4 using 1{

if (RI) {RI = 0;

uart_buf[uart_wr++] = SBUF;

uart_wr &= 0x0f;

}

}

The sending program provided to the user first detects the sending end mark. If it is 0, it means that the last sending has not been completed, and the error message 1 is directly returned.

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Otherwise, the information to be sent is sent and the send end flag is cleared. The purpose of designing the sending program in this way is to not limit the sending wait to the bottom layer of the interface, but to give the upper layer an opportunity to decide whether to wait for the end of sending.

u8 uart_put_c(u8 ch){

if (! TI) return 1;

TI = 0;SBUF = ch; return 0;

}

Similarly, the receiving program also gives the upper layer a chance to choose to wait. The receiving function first determines whether the receiving FIFO is empty. If it is empty or the input pointer parameter is wrong, it directly returns an error. Otherwise, it reads data from the FIFO and stores the data to the address pointed to by the pointer, and then returns success.

u8 uart_get_c(u8 *ch){

u8 i;

if (!ch) return 1;

if ((i = (uart_rd+1)&0x0f) == uart_wr) return 1;

uart_rd = i; *ch = uart_buf[i]; return 0;

}

3.3 Flash memory interface

Flash memory access has a special timing, and the internal structure of flash memory is also very different from the specific application requirements. Therefore, the flash memory interface needs to be carefully designed.

The storage structure organization of the K9F4008 flash memory chip is shown in Figure 2.

The storage of K9F4008 flash memory is in blocks, and each chip has 128 blocks. Each block has 32 rows, each row has 4 frames, and each frame contains 32 bytes. The total chip size is 512 KB.

The flash memory initialization function provided by the flash memory interface includes processing for such situations. The initialization function needs to read a block mapping table from the first block of the flash memory. The table subscript is the logical sector, and each item in the table stores the physical block number corresponding to the logical sector. The initialization function performs read and write verification on the flash memory when necessary, and then deletes the bad block from the table. Then it looks for a new good block and fills its number into the table entry corresponding to the logical sector. In this way, the application can only see the continuous sector numbers, but does not know which block the sector corresponds to.

The flash memory interface header file Flash.h is as follows:

#ifndef _K9F4008_H_

#define _K9F4008_H_

void read_log_page(u8 sector,u8 page,u8 xdata *buf);

u8 prog_log_page(u8 sector,u8 page,u8 xdata *buf);

void erase_log_blk(u8 sector);

bit flash_init(void);

#endif

To implement the flash memory interface, the first step is to define the basic operations of the flash memory according to the timing of the manual. Here, the basic operations are implemented by macro definition.

#define W_CMD（cmd_）

bCLE=1; bWE=0; P2=(cmd_); bWE=1; bCLE=0

#define W_ADDR(addr1_,addr2_,addr3_)

bALE=1; bWE=0; P2=（addr1_）; bWE=1;

bWE=0; P2=（addr2_）; bWE=1;

bWE=0; P2=（addr3_）; bWE=1;

bALE=0

#define W_DAT（dat_） bWE=0; P2=（dat_）； bWE=1

#define wait_RB while (! bRB)

#define l2p(x_) fat_tbl[(x_)]

3.4 EEPROM

The internal integrated EEPROM is separated from the program space. The internal DATAFLASH can be used as EEPROM by using ISP/IAP technology, and the erase and write times are more than 100,000 times. EEPROM can be divided into several sectors, each sector contains 512 B. When using, it is recommended to put the data modified at the same time in the same sector, and the data not modified at the same time in different sectors, and it does not have to be full. The erase operation of the data memory is performed by sector.

sfr IAP_DATA = 0xC2; //Flash data register

sfr IAP_ADDRH = 0xC3; //Flash address HIGH

sfr IAP_ADDRL = 0xC4; //Flash address LOW

sfr IAP_CMD = 0xC5; //Flash command register

sfr IAP_TRIG = 0xC6; //Flash command trigger

sfr IAP_CONTR = 0xC7; //Flash control register

Define the EEPROM registers according to the instructions.