Serial interface between C8051F00x and HCMS2964 intelligent dot matrix display

introduction

HCMS2964 is a new generation of dot matrix display produced by AGILENT TECHNOLOGIES. This product has a built-in CMOS integrated circuit that can drive LEDs and can be directly connected to the processor in serial to achieve data transmission. Because of its convenient and fast brightness adjustment, it can be widely used in embedded systems and single-chip microcomputer-controlled instruments, instruments and flight simulation equipment. This article introduces the display principle of HCMS2964 and the driving mode of the display, brightness adjustment and the design of the basic software.

1 HCMS 2964 display

The HCMS2964 module is a dual in-line package. Each HCMS2964 has 12 pins and an internal crystal array and registers. The HCMS2964 drives four illuminated character blocks through a CMOS refresh circuit. The size of each character is 1.8 cm × 1 cm. These characters are made up of 5 columns × 8 rows, a total of 40 bit registers connected end to end. Row0 is not used and therefore does not emit light. Therefore, each character actually consists of 35 pixels.

HCMS2964 has two independent control registers, and the properties of the HCMS2964 module can be set by changing the contents of the registers. Control register 0 is used for PWM brightness pulse width adjustment, peak current intensity setting (brightness adjustment) and sleep mode control. Control register 1 is used to set the data output mode and crystal array selection mode (select the array frequency or 1/8 of the array frequency). The content of the 160-bit dot register in each display module corresponds to the driving LED and is unique, so the dot register can be directly set to 1 or 0, and the brightness or darkness of the light pixels on the dot matrix can be controlled through the internal IC circuit to form the corresponding characters.

2 System Hardware Interface Settings

The input pins of HCMS2964 should be connected to the I/O port of the microcontroller after being pulled up. The main control pins are RS, CE, and CLK. When designed, they can correspond to P1.0, P1.1, and P1.2 of C8051F00x respectively. RS is used to select the dot matrix display register (L) or the command register (H). The specific timing is that CE must be pulled low before writing the display data, and the corresponding register is selected by RS. The input clock is used to write the dot matrix register or the command register, and can trigger data reading on the rising edge. During the entire process of data transmission, CE must always remain at a low level, and finally the data display output is latched by the CLK clock being low and CE being high (dot register) or rising edge (command register). The functions of the above three pins are listed in Table 1, and the corresponding timing diagram is shown in Figure 1. [page]

3 Cascade

Cascading is mainly used to expand the display part of the system so that more display devices can be hung on the serial expansion interface line. During design, the chip select signal input terminal can be controlled by a single-chip microcomputer, and multiple chip select signals are usually connected together for unified control. The output pin of each display module is connected to the input pin of the next display screen, so that the cascade of multiple display modules can be realized. The specific connection is shown in Figure 2. Generally, in a multi-module cascade display system, the first display module is used to control the four characters on the left, and the last display module is used to control the four characters on the right. The length of the data conversion register is 160 bits × N (the number of N is the number of cascades), and the position 0 of each module is (N-1) × 160 bits, and so on.

The five control buses CE, RS, BL, RST, and CLK should eventually be connected to the I/O lines of C8051f00×. The DIN from the port line is connected to the leftmost module, and the DOUT line is connected to the DIN of the next display module. The DOUT of the last module is idle. Each module can use an internal crystal array or an external crystal array. The SEL high level of the leftmost module of this system is generated by the internal crystal array (MASTER) of the IC, and the SEL low level of other modules is received from the crystal array (SLAVE) of the leftmost module. This system can complete crystal array transmission through the OCS bus.

4 40 levels of brightness adjustment

The dot matrix HCMS2964 series IC provides two ways to change the brightness, namely 16-level and 4-level brightness adjustment, which are achieved by changing the control register 0. Figure 3 is a schematic diagram of its brightness change mode. Among them, PWM brightness control uses DO~D3 of control word 0 and changes the brightness of the dot matrix through real-time pulse width adjustment. Generally, PWM adjusts the pulse width by adjusting the clock cycle of crystal vibration to change the brightness. The peak pixel current control uses D4 and D5 of control word 0 and changes the brightness of the dot matrix by changing four peak pixel currents.

These two ways of changing brightness are suitable for graded brightness adjustment, but in fact, we often encounter the situation of achieving continuous brightness adjustment by collecting the analog value of the potentiometer. At this time, since the brightness collection of the above two methods is only 16 levels or 4 levels, the current jump through the point light source in the circuit between each level is large, and the brightness step change is also more obvious. This brightness step will form an overly obvious brightness mutation visually, so the visual effect is poor. To make the brightness adjustment continuous and soft and more easily accepted by the human eye, only by increasing the number of levels and improving the resolution can the effect achieved by continuous brightness adjustment be simulated. [page]

Since D4-D5 (peak pixel current) and D0-D3 (PWM brightness adjustment) occupy the lower six bits of control word 0, it is possible to consider all the factors that control brightness when designing, and reorganize them according to the brightness to form 4×16=64 levels (i.e. 64 brightness levels) to improve the brightness adjustment effect. It should be noted here that since the brightness collected from 000000H to 111111H is not increasing, the analog quantity should not be collected and directly sent to the lower six bits of the control word, and the pulse width value and the pixel current peak value cannot be simply accumulated to compare the brightness. Experiments have proved that the formula MX=brightness is only valid when one of M and X is a constant and the other is a variable, and it cannot be applied to the multiplication of two variables. The author has arranged their light energy from small to large through the analysis of optical instruments, and screened out mutations and similar energy values, thus forming a 40-level software dimming solution. For the convenience of readers, the 40-level dimming solution is listed in Table 2.

5 System Software Design

The software design of this system can be divided into three parts: display module, analog quantity acquisition module, and serial communication module. The software flow is shown in Figure 4. The dot matrix system control word and display subroutine are as follows:

6 Conclusion

The serial data transmission display system using embedded processor and dot matrix chip given in this paper has simple hardware structure, no need to increase pins, and the system is easy to expand. However, through the actual application of the system, it is found that there are two major problems with serial devices: one is that the speed of serial transmission is slower than parallel transmission, and the other is that serial transmission requires a certain communication protocol, including the communication of equipment, the format of data, and the start and stop of data transmission.