MCU sleep-reset operation mode can improve anti-interference ability

introduction

With the rapid development of microelectronics technology, the performance of single-chip microcomputers has improved rapidly, showing extraordinary advantages in operation, logic control, and intelligence. It has largely replaced the detection and control circuits originally composed of digital logic circuits and operational amplifier circuits, and has been widely used. However, due to its fatal defects such as crashes and program runaway, its application in many important occasions is limited. Many technologies in anti-interference, such as setting software traps and adding hardware watchdog circuits, can solve this problem better, but there are still problems: ① When the watchdog is activated, it means that an error has occurred and has been running for a period of time, which is not allowed in some occasions; ② Sometimes the program has a dead loop error, but it just happens to include the watchdog control link. For such errors, the watchdog cannot be identified; ③ In systems with a long detection and control cycle, the single-chip microcomputer spends a lot of time waiting for peripherals, and will also be disturbed when executing the waiting command. In response to these situations, we have tried the method of active reset in practice, using equally spaced pulses or resetting and waking up the single-chip microcomputer according to external conditions. After each reset, the single-chip microcomputer executes the corresponding program, and enters sleep in time after completing the task, waiting for the next reset. This method solves the above problems well and achieves good results in the experiment of agricultural transformer comprehensive protector. The following takes the 51 series single-chip microcomputer as an example to discuss the specific principle and implementation method, and the reset signal is high level.

1 Principle and implementation method

1.1 Unconditional timed reset method

Use a timer, a dedicated clock chip or other pulse generator to generate a reset signal at a set interval. This method is particularly suitable for monitoring instruments. In actual operation, an A/D converter is often used to sample the input analog quantity, and then store and display it. This process is very fast, but in order to stabilize the reading, the data is updated only 1 to 2 times per second, and a lot of CPU time is spent waiting. If the CPU is allowed to enter sleep directly after completing the task, and then wake it up by an external reset to perform the next operation, this is the timed reset method. This will greatly enhance the anti-interference ability, mainly for two reasons: ① When in sleep mode, the program stops running, and the program will not run away due to the disorder of the PC pointer. If the ratio of working to sleeping time is 1:9, that is, 0.1s of time is used for detection and display in 1s, and 0.9s of time is spent in sleep mode, the probability of the program being interfered is 1/10 of that when running at full speed, and the overall anti-interference ability is improved by 10 times. ② Since it is reset unconditionally once every 1s, once a crash occurs during a certain operation, it will definitely be restored at the next reset. For an instrument that only displays, an occasional reading error in a certain 1 second is not remembered for the next measurement and is tolerable. It is a "transient" error. The advantages of this timed reset over the watchdog circuit are, first, changing the waiting time to a dormant state, shortening the time that may be disturbed; second, avoiding an infinite loop that happens to include the watchdog control link.

1.2 External Condition Reset Method

The start of some outputs or measurements is controlled externally. For example, the heating meter calculates the heat by the pulses generated by the rotation of the hot water wheel. If there is no hot water flow, there is no heat output. The CPU only needs to maintain the original value and does not need to count. It can be imagined that when the heating is stopped, the hot water wheel does not rotate, and the CPU has nothing to do in spring, summer and autumn. If it is put into sleep mode instead of constantly detecting the presence of the water wheel pulse, the anti-interference ability will be greatly enhanced. Therefore, as long as the water wheel pulse is linked to the CPU reset, the CPU resets once every rotation of the water wheel, and the heat meter can work normally. This is the external condition reset method. Similar applications include semi-electronic watt-hour meters, which count once when the mechanical dial rotates once. If the user does not use electricity, the CPU will remain in sleep mode. The reset interval of this method is not fixed, but is determined according to external conditions. In some occasions, the sleep time can be very long, which is very effective in improving the anti-interference ability.

2 Key points of hardware implementation

2.1 Unconditional timed reset

Generally, there are two methods. ① Use a timer or a dedicated clock chip to reset. Figure 1 shows a timing circuit composed of a 555 circuit; you can also use a clock chip such as X1126, set the alarm time and use the alarm signal to wake up the CPU. This method is suitable for long-interval timing, and can also temporarily determine the next alarm wake-up time based on the result of this operation, which is very flexible and convenient. ② Use the system's inherent signal as a timing reset pulse. For example, using a 50Hz industrial frequency power supply after shaping for reset, not only omitting the timer, but also collecting the corresponding signal for detecting the phase of the current signal, as shown in Figure 2.

2.2 External Condition Reset

??Shape the external condition pulse and send it to the reset terminal. For the pulses generated by the water wheel or the meter dial, a Schmitt trigger can be used for shaping; for instruments that record the maximum or minimum value, a window comparator can be used. In order to realize the electronic adjustment, an electronic potentiometer can be used, and the upper and lower limits can be set by the microcontroller instructions.

2.3 Reset cycle and reset high level time

In Figure 3, during the high level Tr period of the reset signal, the microcontroller is in a reset state, the program does not run, and the anti-interference ability is the strongest; after the high level, the microcontroller starts to execute the program. In other words, the low level Td period of the reset signal is the time available for program execution, and this time must be greater than the execution cycle of each program. It is very important to reasonably select the reset cycle and the high level duty cycle of the reset signal. For a simple display instrument, the reset cycle determines the data refresh cycle, and the low level time must be greater than the total time for detection and display; otherwise, there will be an error that the program can never be fully executed. The microcontroller can effectively resist interference during Ts and Tr, but it is better to arrange the extra time in Tr. When the program execution time is long and Tr is required to be shortened as much as possible, a differential circuit can be added, such as C30, R26, and D9 in Figure 1.

2.4 Output terminal processing

(1) Positive pulse during reset

During the reset period, all I/O ports of the microcontroller become high level. In other words, the pins that normally output low will have a positive pulse with a width of Tr according to the reset cycle. This positive pulse will affect the normal output. There are two ways to deal with it: ① Connect a capacitor in parallel to the terminal to suppress it. The capacity is determined according to the reset Tr time. Reducing Tr can reduce the parallel capacitance. ② Design the peripheral circuit to be invalid at high level.

(2) Fault Tolerance

By properly selecting the capacity of the parallel capacitor at the output end, fault-tolerant control can be achieved. In a certain reset cycle, an error level is output due to interference. Due to the holding effect of the capacitor, the output cannot be changed to a valid level in this cycle; in the next cycle, the error is corrected. Therefore, as long as the error does not occur for two consecutive cycles, the output is fault-tolerant. Of course, this method will cause the normal output change to lag for one cycle before it is truly reflected in the output terminal.

2.5 Power-on detection and manual reset

Some systems need to do some initialization operations when they are powered on for the first time. When running in reset mode, each reset has become the starting condition for normal operation, and it is impossible to distinguish whether it is the first time to power on. Connect a 1μF capacitor to the ground on a certain pin, and detect the pin after reset. If it is low level, it is the first time to power on. If a reset button is set for the system, which is the common manual reset, this button is not connected to the reset terminal, but in parallel to the two ends of the capacitor between the above pin and the ground. 3 Key points of software implementation

3.1 Output recovery and non-clearing RAM

After the timed reset, all pins become high level, which makes the pins that should be low change unexpectedly. Therefore, the status of all pins should be restored immediately after the reset. There are two methods: ① Analyze and judge immediately after the reset, and give the pin status as needed; ② According to the status retained in the RAM last time, these RAMs cannot be cleared during the timed reset; but they should be cleared when the power is first turned on or the manual reset is pressed, which should be reflected in the software compilation. If the calculation time allows, try to adopt method 1. Because the probability of calculating errors for two consecutive reset cycles is very small, according to the processing method of the output terminal parallel capacitor described in 2.4, a good anti-interference effect can be achieved.

3.2 Implementing timing control across the timer reset interval

Now we work in reset mode, and execute the same program repeatedly from the beginning each time. It can be divided into two situations: ① For simple display instruments, measurement and display are performed after each reset. There is no causal relationship between the two resets. Just change the original waiting to sleep. It should be noted that the total time used for measurement and display should be less than the reset low level time, otherwise there will be an error that the program can never be fully executed. ② For applications with timing control, after each reset, you must first check the flag left by the previous cycle to decide what to do in this cycle. In other words, all operations that cross the reset cycle are transmitted by flags. These flags are stored in the internal RAM and are only cleared when the power is first turned on. For example, the transformer integrated protector mentioned above is reset at intervals of 20ms. After power-on, it reaches a normal working state after a certain sequence of actions, as shown in Figure 4; a part of the software process is written based on this action, as shown in Figure 5.

In Figure 4, when the protector is powered on for the first time, it first tests power for 0.5s, prompting that power will be supplied immediately; wait for 30s before officially supplying power. The 1s after power supply is the startup time, and no overcurrent detection is performed. After the startup is completed, if everything is normal, the "normal flag" is set, and the protector enters normal operation in the next reset cycle. The 0.5s delay of the test power supply is achieved by counting the reset 25 times, because each reset time is 20ms. When the power is first powered on, all internal RAMs are cleared, and the test power supply timing Ts=25 is set before sleeping. After the next reset, the power-on pin is detected again, and it is no longer the first power-on, so the test power supply timing Ts is detected. If Ts≠0, it means that during the power supply delay period, Ts is reduced by 1 and then enters sleep. When Ts-1=0, it should enter the process of waiting for 30s for power outage. Just when Ts decreases to 0, the power outage waiting flag Td=1500. When the program starts again from reset, it detects that Ts=0 but Td≠0, indicating that the power supply test has been passed and it is now in the process of waiting for 30 seconds after power outage. In this way, the whole process is carried out step by step by parameters such as Tr, Td, and Ts. Conclusion

Anti-interference is an important issue in electronic design, especially in single-chip microcomputers. This is because single-chip microcomputers have the particularity of program runaway. The consequence of interference may be a crash, or it may issue various errors or illegal actions before the crash, causing fatal errors in the entire system. Therefore, it is not enough to just ensure that the single-chip microcomputer does not crash. We must also study how to reduce the risk of interference and how to tolerate errors after errors. This article attempts to explore these two aspects. I hope these superficial insights can serve as a starting point and help everyone. I also hope that colleagues will explore together and improve our design level.