Newbie, please help me with CPLD frequency multiplication

hezicheng

Newbie, please help me with CPLD frequency multiplication [Copy link]

Hi guys, please help me. My graduation project needs to reach 200M300M. The teacher said 500M is the best and then output complex PWM. Then I found that MAX II or V can't reach such a high frequency. Then the teacher said to multiply the frequency. Then I went to Taobao to look at the development board. The boss said that because there is no phase-locked loop CPLD, it is impossible to multiply the frequency. Another boss said that it can reach up to 100M at most and I can match the crystal oscillator myself. The teacher doesn't know anything about CPLD. I am so confused now. Please give me some advice. Thank you.

Jacktang

It is best to reach 500M, so high

Phase-locked loop is required

Ask the teacher what the plan is

hezicheng

Jacktang posted on 2021-4-14 07:29 It is best to reach 500M. Such a high speed requires a phase-locked loop. Ask the teacher what solution is available

The teacher now asked me to output the simplest two-phase PWM, with controllable phase shift angle, duty cycle, and frequency, and to give this information through DSP, and to program CPLD to realize PWM output. The whole design is to make up for the poor details of DSP's PWM module, and then asked me to achieve such a high frequency, and to make it stable, and to realize some functions, and let me think about it myself, for example, when the DSP sends these three signals to change or the duty cycle suddenly reaches 0 or 1, the waveform output by CPLD cannot change immediately, but must wait until the cycle ends. This is roughly what it means.

heningbo

I think the crux of the problem lies in 500M.

500M is the clock frequency, or the maximum PWM output is 500M. If it is the latter, the difficulty is extremely high.

If it's the former, you can find an external PLL and configure it yourself.

But the output must be differential, because I have seen that most 200M crystal oscillators have differential input.

Furthermore, can the pins of CPLD recognize such a high-speed frequency signal? That is, can the receiving end recognize it? We need to confirm it.