Interface Design between Single-Chip Microcomputer and Single-Bus A/D Converter DS2450

DS2450 is a single bus four-channel successive approximation A/D converter chip produced by DALLAS. Its input voltage range, conversion accuracy and alarm threshold voltage are all programmable; each channel can use its own memory to store parameters such as voltage range settings, conversion results and threshold voltage. In normal mode, its serial communication rate is 16.3kbps, while the rate in overspeed working mode can reach 142kbps. The on-chip 16-bit cyclic redundancy check code generator can be used to detect the correctness of communication. DS2450 uses an 8-pin SOIC small package. It can be powered by a single 5V power supply or a parasitic power supply. The power consumption of the chip is only 2.5mW when it is working normally, and
25μW when it is idle. Multiple DS2450 or other single bus chips with MicroLAN interface can be connected in parallel. The CPU only needs one port line to communicate with many single bus chips, and it occupies fewer ports of the microprocessor, so it can save a lot of pins and logic circuits.
1 Pin arrangement and internal structure of DS2450
1.1 Pin function
DS2450 adopts 8-pin SOIC package, and its pin function description is as follows:
Pin 1 (VDD): working power supply input terminal;
Pin 2 (N.C): floating pin;
Pin 3 (DATA): serial data input/output terminal;
Pin 4 (GND): ground terminal;
Pin 5 (AIN-A): A-channel analog voltage input terminal;
Pin 6 (AIN-B): B-channel analog voltage input terminal; Pin 7 (AIN-C): C-channel analog voltage input terminal;
Pin 8 (AIN-D): D-channel analog voltage input terminal.
1.2 Internal structure
The internal structure of DS2450 is shown in Figure 1. The 64-bit serial number in the photolithography ROM is photolithography before leaving the factory, which can be regarded as the address serial code of the DS2450. The arrangement of the 64-bit photolithography ROM is: the first 8 bits (20H) are the product type number, the next 48 bits are the serial number of the DS2450 itself, and the last 8 bits are the cyclic redundancy check code of the previous 56 bits (CRC=X8+X5+X4+1); the function of the photolithography ROM is to make the address of each single-bus device different, so that multiple single-bus chips can be hung on one bus.

For a one-line port, other functions cannot be realized before the ROM function is established. The bus controller must first provide a ROM function control command (8 bits) to the DS2450 through the DATA pin. Its 7 function control commands are:
(1) Read ROM, command word [33H];
(2) Match ROM [55H];
(3) Search ROM [F0H];
(4) Skip ROM [CCH];
(5) Conditional search ROM [ECH];
(6) Overspeed skip ROM [3CH];
(7) Overspeed match ROM [69H].
After the overspeed skip ROM or overspeed match ROM command is executed, the serial communication rate can be as high as 142kbps. If multiple devices are connected on one line, these commands can operate on the 64-bit ROM part of each device and select a specific device. Then the next step of A/D conversion control command and read/write memory command is executed on the selected DS2450. All commands or data read/write start from the lowest bit.
1.3 Memory
The DS2450 has 24 connected 8-bit memories, which can be divided into 3 pages, each with 8 bytes. Page 0 is the A/D conversion result memory, and each channel occupies 2 bytes, a total of 16 bits. When the chip is powered on and reset, this page is cleared to 0; Page 1 is the A/D conversion control and status memory; Page 2 is the input high/low limit alarm value memory for each channel.
2 Conversion and read/write control
2.1 Conversion control
The conversion control of the DS2450 first sends out the conversion command word [3CH] serially through its DATA terminal, then sends out the channel selection word and preset control word, and finally starts the A/D converter for conversion. The meaning of each bit of the channel selection word and preset control word of the DS2450 is listed in Table 1.
In the channel selection word, the corresponding bit is 1, indicating that the channel participates in the conversion. When multiple channels are selected at the same time, the conversion order is A→B→C→D, and the unselected channels will be skipped. The time of A/D conversion can be approximated as:
conversion time = number of channels × number of conversion precision bits × 80μs + 160μs.
When all channels are converted, the system will issue a read memory command to obtain the conversion results and corresponding status.
The preset control word can be used to preset the conversion result memory of the corresponding channel. When SET, CLR = 00, it is not preset, that is, the last conversion value is kept; when SET, CLR = 01, it is preset to all 0 before conversion; when SET, CLR = 10, it is preset to all 1; and
SET, CLR = 11 is an invalid combination.

2.2 Memory read/write control
The memory read command can be used to read conversion results, working status, threshold setting values, etc. The bus manager first sends out the memory read command word [AAH], then sends out two bytes of 16-bit "starting data" memory address, and after reading a byte of data on the bus, the address automatically increases by 1, and then reads the next data; when a page is read, the next two bytes read are the 16-bit cyclic redundancy check code automatically generated internally, which is generated by the command word, address and memory data sent previously and according to the following expression:
CRC16＝X16＋X15＋X2＋1The
memory write command is mainly for the first and second pages of memory, and its purpose is to write the working mode control word of each channel and the high and low threshold setting values ​​of the corresponding channel. The bus manager first sends out the memory write command word [55H], then sends out two bytes of 16-bit memory starting address, and then sends out the data to be written one by one, and its address is also automatically increased by 1. If a read operation is performed just after writing a data, the data read out should be exactly the data written last time. This feature can be used to compare the written and read data to determine the correctness of the transmission.
If a transmission error is found in the read/write during the software verification, the DS2450 chip must be initialized and the read/write operation must be performed again.
2.3 DS2450 working sequence
The first-line working protocol flow of the DS2450 is: initialization → ROM function command → memory read/write/conversion control function command → data transmission. Its working sequence includes initialization sequence, write sequence and read sequence. Figure 2 shows the working sequence in normal working mode.
3 Typical interface design of DS2450 and single-chip microcomputer
Figure 3 is a typical connection circuit between MCS-51 series single-chip microcomputer and DS2450. The DATA terminal of DS2450 is connected to P1.0 of AT89C51. The circuit adopts an external power supply mode, and the VCC terminal of DS2450 is powered by a 5V power supply. In this example, only the D channel is converted to A/D. AIN-D is connected to the analog signal input; AIN-A and AIN-B are connected to the power supply with external pull-up resistors, and their outputs can be used as the high and low limit alarm signals of the D channel.
If the crystal frequency used by the microcontroller system is 12MHz, three subroutines can be written according to the initialization timing, write timing, and read timing of the DS2450: INIT is the initialization subroutine, which can be used to send a reset pulse and receive a presence pulse; WRITE is the write (command or data byte) subroutine; READ is the read data subroutine. All commands or data bytes to be read or written are placed in the A register.

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The following steps are generally required to complete A/D conversion by controlling DS2450 through the host: initialization, sending ROM function commands and corresponding 64-bit photolithography ROM data, selecting a specific chip, writing the working mode control word and high/low threshold value, sending conversion control commands, reading conversion values ​​and status, etc.
If the D channel is set to a 5.1V input range, the conversion accuracy is 12 bits, the high alarm threshold is 3.0V (96H), the low alarm threshold is 2.0V (64H), and channel A and channel B are used as alarm outputs, and finally the conversion results are placed at 30H and 31H, then the specific program list of its subroutine CTLAD is as follows:

CTLAD: LCALLINIT; send reset pulse and receive presence pulse





If there are multiple DS2450s and other single bus interface chips on a line, the subroutine CTLAD that uses parasitic power supply and overspeed mode and requires verification during communication may be more complicated to write.