Some suggestions on EMC of microcontrollers

Although this article was written 10 years ago, it still has a lot of practical reference significance. In addition, other IC manufacturers also have a lot of reference documents, if you are interested, you can refer to them. Off topic, this topic is mainly to analyze the main interference sources and sensitive devices inside the module, and slowly understand the EMC design of the module through the design of these main things. However, it is inevitable that there are some superficial suspicions. With more accumulation, it may be easy to consider the problem in the early stage of circuit design in the future.
1. The operating frequency of the microcontroller

1.1 The design of the MCU should choose a lower operating frequency according to the needs of customers
First, let me introduce the advantages of doing so: using low crystal oscillator and bus frequency allows us to choose a smaller MCU to meet the timing requirements, so that the operating current of the MCU can become lower, and most importantly, the current peak from VDD to VSS will be smaller.
Of course, we need to make a compromise here, because the customer's requirements may be compatible and platform-based (the current development trend of automotive electronics is platform-based), and choosing a higher operating frequency can be compatible with more platforms and is also convenient for future upgrades and expansions, so we should choose a lower acceptable operating frequency.

2 Appropriate output drive capability
Given load specifications, rise and fall times, selecting the appropriate output rise time and minimizing the peak current of the output and internal drivers are one of the most important design considerations for reducing EMI. Unmatched drive capability or failure to control the output voltage change rate may result in impedance mismatch, faster switching edges, overshoot and undershoot of the output signal, or power and ground bounce noise.

2.1 Design the output driver of the microcontroller. First, determine the load required by the module, the rise and fall time, the output current and other parameters. According to the above information, the driving capacity and the voltage slew rate are controlled. Only in this way can the module requirements and EMC requirements be met.
When the driver capacity is higher than the actual charging speed required by the load, a higher edge rate will be generated. This will have two disadvantages
: 1. The harmonic components of the signal are increased.
2. Together with the load capacitance and parasitic internal bonding lines, IC packaging, and PCB inductance, it will cause overshoot and undershoot of the signal.
Selecting the appropriate di/dt switching characteristics can be achieved by carefully selecting the size of the driving capacity and controlling the voltage slew rate. The best option is to use a constant voltage slew rate output buffer that is independent of the load. The voltage slew rate of the same pre-driver output can be reduced (that is, the rise and fall time can be increased), but the corresponding propagation delay will increase, and we need to control the total switching time).

2.2 Use the drive capability of the programmable output port of the microcontroller to meet the actual load requirements of the module.
The simplest driver of the programmable output port is a pair of drivers connected in parallel. Their MOS Rdson is different and the output current capacity is also different. We can choose different modes during testing and actual use. In fact, the current microcontrollers generally have at least two modes to choose from, and some can even have three (strong, medium, weak) [page]

2.3 When there is enough margin in the timing constraints, slow down the edge of the internal clock drive by reducing the output capacity.
To reduce the peak current and di/dt of the synchronous switch, an important consideration is to reduce the capacity of the internal clock drive (actually the amplification factor, the penetration current is closely related to it). Reducing the current of the clock edge will significantly improve EMI. Of course, the disadvantage of doing so is that the average current of the microcontroller may increase due to the longer turn-on time of the clock and load. A compromise needs to be made between fast edges and relatively high peak currents, and current pulses with longer times and slower edges.

2.4 The internal drive (inverter) of the crystal oscillator should not exceed the actual demand.
This problem has actually been discussed before. When the gain is too large, it will cause greater interference.

3 Design drivers with minimum through-current
3.1 Clock, bus and output driver should minimize traditional current as much as possible
Through-current [overlap current, short-circuit current] is the current from the power supply to the ground when the PMOS and NMOS are turned on at the same time during the switching process of the microcontroller. Through-current directly affects EMI and power consumption.
This content is actually inside the microcontroller, clock, bus and output driver. The way to eliminate or reduce through-current is to try to turn off one FET first and then turn on another FET. When the current is large, additional pre-drive circuit or voltage slew rate is required.