Design of a controllable imaging system based on 51 single chip microcomputer

0 Introduction
The optical imaging system is an important tool for converting optical information into electronic information that is easier for people to process. It is particularly important for intelligent monitoring, medical diagnosis and consumer electronics. With the complexity of the imaging system functions, the portability and controllability of the camera have become important factors to be considered in the design. Since Willard S. Boyle and George E. Smith invented the charge-coupled device (CCD) in 1969, it has been the preferred sensor for optical imaging systems. Compared with the currently developed fast CMOS image sensors, it still has the advantages of low noise and high dynamic range. The analog front end of the CCD determines the quality of the collected signal and has a decisive influence on the signal-to-noise ratio of the entire system. Therefore, its noise suppression is the focus of the design. The module that completes various image processing functions is the core of the imaging system. In view of the design requirements of low-light video signal imaging, professional signal processing chips are used for various processing. The signal processing chip (DSP) is parameterized through the single-chip microcomputer (MCU) to complete the control of various complex computing functions, simplifying the logical design of the system and making it have good controllability.

1 System composition
The system consists of CCD, analog front end AFE (including correlated double sampling CDS and automatic gain control AGC), signal processing module, microprocessor module and analog digital output module. The system block diagram is shown in Figure 1.

The CCD sensor in the figure is the basis of the entire system. External optical signals can only be processed through photoelectric conversion. The analog signal output by the sensor will be amplified by the front end and enter the AFE in the form of differential input. Then, through a series of analog signal noise reduction and amplification processing (CDS, AGC), it enters the signal processing module for various calculations. The signal processing module is a bridge connecting the CCD output and the back-end general equipment. The professional signal processing chip provides a large number of video processing calculation functions and a variety of video output formats, which brings convenience to subsequent processing. Through various DSP processing, the chromaticity, brightness and saturation images required by the design are obtained, and finally the analog or digital signals compatible with the terminal format are output. The analog output can be directly connected to the monitor, and the digital output can be connected to the VGA, DVI interface display through FPGA, ASIC and other devices. [page]

2 Analog front-end module
The noise of CCD readout circuit mainly includes the inherent noise of the devices used in the readout circuit, as well as the additional noise introduced by the circuit structure and circuit working mode. There are mainly 1/f noise, KTC noise and fixed plane noise, which limit the dynamic range of the image sensor and reduce the signal-to-noise ratio. In the readout circuit, the correlated double sampling technology (CDS) is currently the most widely used noise suppression technology. Since the reset noise in the transmission time of a pixel is correlated, the correlated double sampling circuit (CDS) can use the signal subtraction operation relationship to eliminate or weaken the 1/f noise, KTC noise and fixed plane noise in the signal, thereby greatly improving the signal-to-noise ratio of the system. The automatic gain control circuit (AGC) can make the gain of the amplifier circuit automatically adjust with the signal strength, so that the brightness of the image signal is stable, especially the amplification of weak light signals in low-light environments. But the disadvantage is that it will also amplify the dark current under low-light conditions, reducing the image quality. In addition, the reasonable selection of the analog front-end bandwidth can compromise the system noise and the system modulation transfer function to meet the needs of the application. There are currently two AFE design methods, one is to use discrete components, and the other is to use integrated AFE chip experiments. As the AFE chip matures, it also integrates a dark current correction circuit, and its various indicators are much higher than the circuit built with general discrete components, and it is easy to debug. The integrated AFE selected for this system is CXA2096N, which is specially designed for digital cameras. It includes a correlated double sampling circuit (CDS), an automatic gain control circuit (AGC), a reference level for the A/D converter, and a sample-and-hold circuit. Its automatic gain range is -0.8 to 31.3 dB.

3 Signal processing module
3.1 Video processing chip
The signal processing chip selected in this article is SONY's CXD3172AR. The chip has a built-in 10-bit high-precision A/D converter, with functions such as automatic white balance, automatic exposure, automatic black level correction and defect compensation, and can generate timing pulses to drive CCD. It can output analog signals in PAL/NTSC format and digital signals in ITU656 format. There are two control methods: PC software control through RS 232 interface; direct hardware control through MCU general pins. Because the transmission bus of MCU does not belong to the general I2C and SPI bus, the communication interface with MCU is designed with reference to chip data. The maximum transmission rate supported by the chip is 400 Kb/s; using PC software only supports 19.2 Kb/s, and the bandwidth of the chip cannot be fully utilized. Software control must also rely on PC, which is not conducive to portability. In this system, the DSP function implemented by pure hardware control is fast and flexible. The peripheral circuits of the signal processing module with CXD3172AR as the core mainly include power supply, clock, video output interface and control communication interface.
3.2 Clock generation circuit
CXD3172AR needs to generate timing pulses to drive CCD, and its main clock will affect the normal and stable operation of the entire system. The CCD selected by the system is compatible with PAL color cameras, with a total pixel of 795 (H) × 596 (V). The system requires a 28.375 MHz clock drive system and a 27 MHz clock drive codec. In order to have a stable clock source, a phase-locked loop (PLL) is used to compare the phase of a frequency division of a high-stability reference source with a frequency division of VCXO, generate an error change voltage, and give negative feedback to the VCXO loop, so as to make the output frequency more stable. The VCXO is designed to output a 28.375 MHz clock and the quartz crystal oscillator circuit outputs a 27 MHz clock. The horizontal synchronization signal frequency generated by the system is 15.625 kHz, which is compared with the frequency division of VCXO in phase. The PCOMP pin outputs the phase comparison result to determine whether the phase is locked.
3.3 Power supply
circuit The system requires 4 independent power supplies, with voltages of 3.3 V, 5 V, 15 V, and -7 V. Considering portability, a 9 V DC voltage is used as the input of the circuit board. The 3.3 V and 5 V voltages are obtained through the linear voltage regulator chips LT1117-3.3 and LT1117-5, and the 15 V and -7 V voltages are obtained by selecting TPS65131. TPS65131 can output positive and negative dual voltages, which is very suitable for portable devices. The output ends of the 4 power supplies are respectively passed through LC low-pass filters to provide the system with high-precision and stable DC power.

[page]

3.4 Video output circuit
CXD3172AR can output PAL analog signals. Its input port adopts current output structure and generates signal voltage through resistance. However, due to the existence of system noise, especially the interference of analog ground and digital, signal wiring length, component layout and other factors, a filter can be added to the output end to improve the signal-to-noise ratio. For the brightness signal, the chip has integrated LPF at the output end, so only the chrominance signal needs to be processed. Set DSP to output Y/C separation signal. The bandwidth of the video signal is generally 6 MHz, and the subcarrier frequency of the chrominance signal is (4.43±1.3 MHz). Figure 2 is the frequency characteristic diagram of the chrominance BPF. The brightness signal and the chrominance signal passing through the BPF enter the video signal mixing amplifier NJM2274, whose output impedance is 75 Ω. The amplified signal can be directly input to the monitor.

3.5 MCU-DSP Communication
DSP processing functions can be controlled by MCU or software. The DSP control parameters are transmitted to the DSP internal register or external E2PROM through a specific communication protocol to realize various processing functions of the video signal. The MCU here is STC's STC89C52RC chip, and it is equipped with basic hardware circuits to make it a minimum system. The DSP control parameters are 635 B. During debugging, they can be stored in the DSP register group for modification. After debugging, the optimized parameters can be stored in the E2PROM so that they can continue to be used after the next power-off reset.
During the communication process, the number of bytes transmitted by a communication protocol packet is variable, up to 32 B. After receiving a packet of data, the DSP analyzes it, executes the control command, and completes one communication. A communication packet consists of a start word, a command word, an address word, and a data word. Because the number of internal registers of the DSP is limited, no other control commands will be received before the last command is executed. This process is called the "communication disable cycle", and at this time, the chip returns a confirmation data, which may be a write response signal, read data, or a communication error code. Its chip select signal, clock signal and input/output signal format are shown in Figure 3.

3.6 Interface between MCU and DSP
When communicating data between different hardware interfaces, the logic level must be consistent, otherwise various unpredictable errors will occur during the communication process. In this design, the main power supply VDD of CXD3172AR is 3.3 V, its logic high level is greater than or equal to 0.7 VDD, and its logic low level is less than or equal to 0.2 VDD, which belongs to LVTTL level. The general MCU pin is generally TTL level, so the communication between the two must be level converted. Here, SN74ALVC164245 is selected as the level converter. SN74ALVC164245 has 2 sets of independent power ports, which are connected to the main power supply of MCU and DSP respectively. In this way, the 3.3 V system and the 5 V system can be connected through the level converter.

[page]

4 Simulation and debugging
Figure 4 is a software simulation diagram. The input data is transmitted low first. Each byte has 8 bits. There is a delay of 1 clock cycle between bytes. The DSP samples the input data at the rising edge of the clock and outputs the data at the falling edge of the clock. The selection signal XCS is valid at low level. In order to meet the system's certain timing redundancy, XCS is forced to be set high during the DSP processing time (i.e., the communication prohibition cycle). Due to software simulation, DO has no waveform. However, in order to be able to test whether the communication is successful, a readback display function is added to the program. Two hexadecimal readback data are displayed through four 7-terminal digital display tubes to determine whether the communication is successful.

At the same time, referring to several basic functions of DSP, its control parameters are saved in the program code. Through the selection of external switches, the P1 port of MCU reads its level to realize the control of various functions. Its functions are shown in Table 1.

After completing the design and debugging of each part of the circuit board, experiments were carried out. The results showed that the MCU-DSP communication was normal and could meet the timing and functional requirements.

5 Conclusion
The controllable imaging system design was realized by using professional signal processing chips and single-chip microcomputers, and the debugging and functional experiments of the circuit board were completed, providing source image signals for subsequent digital signal processing. The system has simple and reliable circuit implementation, convenient function control, and can output signals in multiple video formats, with simple flexibility. At present, the system has been used in the inter-frame filtering technology acquisition system in low-light environments, with good results.